Fec Top-Level Functional Diagram; Fec Block Diagram - Motorola ColdFire MCF5281 User Manual

FEC Top-Level Functional Diagram

17.3 FEC Top-Level Functional Diagram
The block diagram of the FEC is shown below. The FEC is implemented with a
combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant
with industry and IEEE 802.3 standards.
SIF
Bus
Controller
Descriptor
Controller
(RISC +
microcode)
MII
MDO
MDEN
MDI
I/O
PAD
EMDIO EMDC
The descriptor controller is a RISC-based controller that provides the following functions
in the FEC:
• Initialization (those internal registers not initialized by the user or hardware)
• High level control of the DMA channels (initiating DMA transfers)
• Interpreting buffer descriptors
• Address recognition for receive frames
• Random number generation for transmit collision backoff timer
17-4
CSR
RAM
RAM I/F
MIB
Counters
Figure 17-1. FEC Block Diagram
MCF5282 User's Manual
FIFO
Controller
Transmit
Receive
ETXEN ETCLK
ETXD[3:0]
ECRS,ECOL
ETXER
MII/7-WIRE DATA
OPTION
DMA
FEC Bus
ERXCLK
ERXDV
ERXD[3:0]
ERXER
MOTOROLA