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electrical characteristics
absolute maximum ratings, 33-7
operating conversion specifications, 33-9
operating electrical specifications, 33-7
external multiplexing, 27-31
operation, 27-32
options, 27-34
features, 27-1
interrupts
operation, 27-75
sources, 27-76
leakage, 27-75
memory map, 27-7
operation
continuous-scan, 27-54
externally gated, 27-56
externally triggered, 27-56
periodic timer, 27-57
software-initiated, 27-55
debug mode, 27-3
disabled, 27-50
low-power modes, 7-12
reserved, 27-50
single-scan, 27-50
externally gated, 27-52
externally triggered, 27-52
interval timer, 27-53
software-initiated, 27-51
stop mode, 27-3
overview, 27-1
periodic/interval timer, 27-58
QCLK generation, 27-57
queue priority, 27-38, 27-40
registers
control 2–0 (QACRn), 27-11–27-16
conversion command word (CCW), 27-26, 27-59
left-justified signed result (LJSRR), 27-30
left-justified unsigned result (LJURR), 27-30
module configuration (QADCMCR), 27-8
port data (PORTQA and PORTQB), 27-9
port QA and QB data direction (DDRQA,
DDRQB), 27-10
result word table, 27-62
right-justified unsigned result (RJURR), 27-29
status 0–1 (QASRn), 27-19, 27-26
successive approximation (SAR), 27-37
test (QADCTEST), 27-9
result coherency, 27-31
stress conditions, 27-69
timing diagrams
conversion in gated mode, continuous scan, 27-67
conversion in gated mode, single scan, 27-66
conversion timing, 27-36
conversion timing, bypass mode, 27-36
Index-10
INDEX
QSPI
baud rate selection, 22-6
description, 22-1
electrical characteristics
AC timing specifications, 33-24
features, 22-1
interface, 22-2
operation
low-power modes, 7-9
master mode, 22-3
overview, 22-1
programming
example, 22-16
model, 22-9
RAM
command, 22-6
model, 22-4
receive, 22-5
transmit, 22-6
registers
address (QAR), 22-14
command RAM (QCRn), 22-15
data (QDR), 22-14
delay (QDLYR), 22-11
interrupt (QIR), 22-13
mode (QMR), 22-10
wrap (QWR), 22-12
timing diagram, 33-24
transfer
data, 22-8
delays, 22-7
length, 22-8
R
Registers
cache
access control 1–0 (ACRn), 2-8, 4-11
control (CACR), 2-8, 4-4, 4-7
chip configuration module
chip configuration (CCR), 30-5
chip identification (CIR), 30-8
reset configuration (RCON), 30-6
chip select module
address (CSARn), 12-6
control (CSCRn), 12-8
mask (CSMRn), 12-7
clock module
synthesizer control (SYNCR), 9-6
synthesizer status (SYNSR), 9-8
ColdFire Flash module
clock divider (CFMCLKD), 6-10
command (CFMCMD), 6-16
configuration (CFMCR), 6-9
data access (CFMDACC), 6-14
MCF5282 User's Manual
MOTOROLA
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