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8.4.5
Core Watchdog Service Register (CWSR)
The software watchdog service sequence must be performed using the CWSR as a data
register to prevent a CWT time-out. The service sequence requires two writes to this data
register: first a write of 0x55 followed by a write of 0xAA. Both writes must be performed
in this order prior to the CWT time-out, but any number of instructions or accesses to the
CWSR can be executed between the two writes. If the CWT has already timed out, writing
to this register has no effect in negating the CWT interrupt. Figure 8-5 illustrates the
CWSR. At system reset, the contents of CWSR are uninitialized.
Field
Reset
R/W
Address
Figure 8-5. Core Watchdog Service Register (CWSR)
8.5
Internal Bus Arbitration
The internal bus arbitration is performed by the on-chip bus arbiter, which containing the
arbitration logic that controls which of up to four MBus masters (M0–M3 in Figure 8-6)
has access to the external buses. The function of the arbitration logic is described in this
section.
MOTOROLA
7
IPSBAR + 0x013
Chapter 8. System Control Module (SCM)
CWSR[7:0]
Uninitialized
R/W
Internal Bus Arbitration
0
8-9
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