Mii Transmit Signal Timing (Etxd[3:0], Etxen, Etxer, Etxclk); Mii Receive Signal Timing Diagram; Mii Receive Signal Timing - Motorola ColdFire MCF5281 User Manual

33.12.1 MII Receive Signal Timing (ERXD[3:0], ERXDV,
ERXER, and ERXCLK)
The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the ERXCLK frequency.
Table 33-17 lists MII receive channel timings.
Num
M1 ERXD[3:0], ERXDV, ERXER to ERXCLK setup
M2 ERXCLK to ERXD[3:0], ERXDV, ERXER hold
M3 ERXCLK pulse width high
M4 ERXCLK pulse width low
1
ERXDV, ERXCLK, and ERXD[0] have same timing in 10 Mbps 7-wire interface mode.
Figure 33-10 shows MII receive signal timings listed in Table 33-17.
ERXCLK (input)
ERXD[3:0] (inputs)
ERXDV
ERXER
Figure 33-10. MII Receive Signal Timing Diagram
33.12.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN,
ETXER, ETXCLK)
The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the ETXCLK frequency.
The transmit outputs (ETXD[3:0], ETXEN, ETXER) can be programmed to transition
from either the rising or falling edge of ETXCLK, and the timing is the same in either case.
This options allows the use of non-compliant MII PHYs. Refer to the Ethernet chapter for
details of this option and how to enable it.
MOTOROLA
Table 33-17. MII Receive Signal Timing
1
Characteristic
M1 M2
Chapter 33. Electrical Characteristics
Fast Ethernet AC Timing Specifications
Min
5
5
35%
35%
M3
M4
Max Unit
— ns
— ns
65% ERXCLK period
65% ERXCLK period
33-21