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Chapter 4
Cache
This chapter describes the MCF5282 cache operation.
4.1
Cache Features
• Configurable as instruction, data, or split instruction/data cache
• 2-Kbyte direct-mapped cache
• Single-cycle access on cache hits
• Physically located on the Coldfire core's high-speed local bus
• Nonblocking design to maximize performance
• Separate instruction and data 16-Byte line-fill buffers
• Configurable instruction cache miss-fetch algorithm
4.2
Cache Physical Organization
The cache is a direct-mapped single-cycle memory. It may be configured as an instruction
cache, a write-through data cache, or a split instruction/data cache. The cache storage is
organized as 128 lines, each containing 16 bytes. The memory storage consists of a
128-entry tag array (containing addresses and a valid bit), and a data array containing 2
Kbytes, organized as 512 x 32 bits.
Cache configuration is controlled by bits in the cache control register (CACR) that is
detailed later in this chapter. For the instruction or data-only configurations, only the
associated instruction or data line-fill buffer is used. For the split cache configuration,
one-half of the tag and storage arrays is used for an instruction cache and one-half is used
for a data cache. The split cache configuration uses both the instruction and the data line-fill
buffers. The core's local bus is a unified bus used for both instruction and data fetches.
Therefore, the cache can have only one fetch, either instruction or data, active at one time.
For the instruction- or data-only configurations, the cache tag and storage arrays are
accessed in parallel: fetch address bits [10:4] addressing the tag array and fetch address bits
[10:2] addressing the storage array. For the split cache configuration, the cache tag and
storage arrays are accessed in parallel. The msb of the tag array address is set for instruction
fetches and cleared for operand fetches; fetch address bits [9:4] provide the rest of the tag
MOTOROLA
Chapter 4. Cache
4-1
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