Table of Contents
Advertisement
Functional Description
DMA timer operation is disabled in stop mode, but the DMA timer is unaffected by either
the wait or doze modes and may generate an interrupt to exit these modes. Upon exiting
stop mode, the timer will resume operation unless stop mode was exited by reset.
7.3.2.12 Interrupt Controllers (INTC0, INTC1)
The interrupt controller is not affected by any of the low-power modes. All logic between
the input sources and generating the interrupt to the processor will be combinational to
allow the ability to wake up the CPU processor during low-power stop mode when all
system clocks are stopped.
An interrupt request will cause the CPU to exit a low-power mode only if that interrupt's
priority level is at or above the level programmed in the interrupt priority mask field of the
CPU's status register (SR). The interrupt must also be enabled in the interrupt controller's
interrupt mask register as well as at the module from which the interrupt request would
originate.
7.3.2.13 Fast Ethernet Controller (FEC)
In wait and doze modes, the FEC may generate an interrupt to exit the low-power modes.
• Clearing the ECNTRL[ETHER_EN] bit disables the FEC function.
• The FEC is unaffected by wait mode and may generate an interrupt to exit this mode.
In stop mode, the FEC stops immediately and freezes operation, register values, state
machines, and external pins. During this mode, the FEC clocks are shut down. Coming out
of stop mode returns the FEC to operation from the state prior to the low-power mode entry.
7.3.2.14 I/O Ports
The I/O ports are unaffected by entry into a low-power mode. These pins may impact
low-power current draw if they are configured as outputs and are sourcing current to an
external load. If low-power mode is exited by a reset, the state of the I/O pins will revert to
their default direction settings.
7.3.2.15 Reset Controller
A power-on reset (POR) will always cause a chip reset and exit from any low-power mode.
In wait and doze modes, asserting the external RSTI pin for at least four clocks will cause
an external reset that will reset the chip and exit any low-power modes.
In stop mode, the RSTI pin synchronization is disabled and asserting the external RSTI pin
will asynchronously generate an internal reset and exit any low-power modes. Registers
will lose current values and must be reconfigured from reset state if needed.
7-10
MCF5282 User's Manual
MOTOROLA
Advertisement
Table of Contents
