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Functional Description
To transmit a pause frame, the FEC must operate in full-duplex mode and the user must
assert flow control pause (TCR[TFC_PAUSE]). On assertion of transmit flow control
pause (TCR[TFC_PAUSE]), the transmitter asserts TCR[GTS] internally. When the
transmission of data frames stops, the EIR[GRA] (graceful stop complete) interrupt asserts.
Following EIR[GRA] assertion, the pause frame is transmitted. On completion of pause
frame transmission, flow control pause (TCR[TFC_PAUSE]) and TCR[GTS] are
deasserted internally.
The user must specify the desired pause duration in the OPD register.
Note that when the transmitter is paused due to receiver/microcontroller pause frame
detection, transmit flow control pause (TCR[TFC_PAUSE]) still may be asserted and will
cause the transmission of a single pause frame. In this case, the EIR[GRA] interrupt will
not be asserted.
17.4.11 Inter-Packet Gap (IPG) Time
The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After
completing a transmission or after the backoff algorithm completes, the transmitter waits
for carrier sense to be negated before starting its 96 bit time IPG counter. Frame
transmission may begin 96 bit times after carrier sense is negated if it stays negated for at
least 60 bit times. If carrier sense asserts during the last 36 bit times, it will be ignored and
a collision will occur.
The receiver receives back-to-back frames with a minimum spacing of at least 28 bit times.
If an inter-packet gap between receive frames is less than 28 bit times, the following frame
may be discarded by the receiver.
17.4.12 Collision Handling
If a collision occurs during frame transmission, the Ethernet controller will continue the
transmission for at least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If
the collision occurs during the preamble sequence, the JAM pattern will be sent after the
end of the preamble sequence.
If a collision occurs within 512 bit times, the retry process is initiated. The transmitter waits
a random number of slot times. A slot time is 512 bit times. If a collision occurs after 512
bit times, then no retransmission is performed and the end of frame buffer is closed with a
Late Collision (LC) error indication.
17.4.13 Internal and External Loopback
Both internal and external loopback are supported by the Ethernet controller. In loopback
mode, both of the FIFOs are used and the FEC actually operates in a full-duplex fashion.
MOTOROLA
Chapter 17. Fast Ethernet Controller (FEC)
17-17
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