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7
Field
RESULT
Reset
R/W:
R/W
Address
Figure 27-17. Left-Justified Unsigned Result Register (LJURR)
Bit(s)
Name
15–6
RESULT
5–0
—
27.7 Functional Description
This subsection provides a functional description of the QADC.
27.7.1 Result Coherency
The QADC supports byte and half-word reads and writes across a 16-bit data bus interface.
All conversion results are stored in half-word registers, and the QADC does not allow more
than one result register to be read at a time. For this reason, the QADC does not guarantee
read coherency.
Specifically, this means that while the QADC is operating, the data in the result registers
can change from one read to the next. Simply initiating a read of one result register will not
prevent another from being updated with a new conversion result.
Thus, to read any given number of result registers coherently, the queue or queues capable
of modifying these registers must be inactive. This can be guaranteed by system operating
conditions (such as, known completion of a software-initiated queue single-scan or no
possibility of an externally triggered/gated queue scan) or by simply disabling the queues
(writing MQ1 and/or MQ2 to 0).
27.7.2 External Multiplexing
External multiplexer chips concentrate a number of analog signals onto a few QADC
inputs. This is useful for applications that need to convert more analog signals than the
QADC converter can normally support. External multiplexing also puts the multiplexed
chip closer to the signal source. This minimizes the number of analog signals that need to
be shielded due to the proximity of noisy high speed digital signals at the microcontroller
chip.
MOTOROLA
6
5
IPSBAR + 0x19_0380, 0x19_03fe
Table 27-20. LJURR Field Descriptions
The conversion result is unsigned, left-justified data.
Reserved, should be cleared.
Chapter 27. Queued Analog-to-Digital Converter (QADC)
—
Undefined
R
Description
Functional Description
0
27-31
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