Motorola ColdFire MCF5281 User Manual page 349

Bits Name
27–25 BWC Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count reaches a multiple
of the BWC value, the DMA releases the bus. For example, if BCR24BIT is 0, BWC is 001 (512 bytes or value
of 0x0200), and BCR is 0x1000, the bus is relinquished after BCR values of 0x0E00, 0x0C00, 0x0A00, 0x0800,
0x0600, 0x0400, and 0x0200. If BCR24BIT is 0, BWC is 110, and BCR is 33000, the bus is released after 232
bytes because the BCR is at 32768, a multiple of 16384.
24-23 — Reserved, should be cleared.
22 SINC Source increment. Controls whether a source address increments after each successful transfer.
0 No change to SAR after a successful transfer.
1 The SAR increments by 1, 2, 4, or 16, as determined by the transfer size.
21–20 SSIZE Source size. Determines the data size of the source bus cycle for the DMA control module.
00 Longword
01 Byte
10 Word
11 Line (16-byte burst)
19 DINC Destination increment. Controls whether a destination address increments after each successful transfer.
0 No change to the DAR after a successful transfer.
1 The DAR increments by 1, 2, 4, or 16, depending upon the size of the transfer.
18–17 DSIZE Destination size. Determines the data size of the destination bus cycle for the DMA controller.
00 Longword
01 Byte
10 Word
11 Line (16-byte burst)
16 START Start transfer.
0 DMA inactive
1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared
automatically after one system clock and is always read as logic 0.
MOTOROLA
Table 16-3. DCRn Field Descriptions (continued)
Encoding
000
001
010
011
100
101
110
111
Chapter 16. DMA Controller Module
DMA Controller Module Programming Model
Description
BCR24BIT = 0
DMA has priority and does not negate its request
until transfer completes.
512
1024
2048
4096
8192
16384
32768
BCR24BIT = 1
16384
32768
65536
131072
262144
524288
1048576
16-9