Table of Contents
Advertisement
• At the completion of cycle 3, the debug module initiates a memory read operation.
Any serial transfers that begin during a memory access return a not-ready response.
• Results are returned in the two serial transfer cycles after the memory access
completes. For any command performing a byte-sized memory read operation, the
upper 8 bits of the response data are undefined and the referenced data is returned in
the lower 8 bits. The next command's opcode is sent to the debug module during the
final transfer. If a memory or register access is terminated with a bus error, the error
status (S = 1, DATA = 0x0001) is returned instead of result data.
29.5.3.3 Command Set Descriptions
The following sections describe the commands summarized in Table 29-17.
The BDM status bit (S) is 0 for normally completed
commands; S = 1 for illegal commands, not-ready responses,
and transfers with bus-errors. Section 29.5.2, "BDM Serial
Interface," describes the receive packet format.
Motorola reserves unassigned command opcodes for future expansion. Unused command
formats in any revision level perform a
29.5.3.3.1 Read A/D Register (
Read the selected address or data register and return the 32-bit result. A bus error response
is returned if the CPU core is not halted.
Command/Result Formats:
15
Command
0x2
Result
Command Sequence:
Figure 29-18.
Operand Data:
Result Data:
MOTOROLA
NOP
RAREG
12
11
0x1
Figure 29-17.
RAREG
RAREG/RDREG
???
RAREG
None
The contents of the selected register are returned as a longword
value, most-significant word first.
Chapter 29. Debug Support
NOTE:
and return an illegal command response.
/
)
RDREG
8
7
0x8
D[31:16]
D[15:0]
/
Command Format
RDREG
XXX
NEXT CMD
MS RESULT
LS RESULT
XXX
NEXT CMD
BERR
'NOT READY'
/
Command Sequence
RDREG
Background Debug Mode (BDM)
4
3
2
A/D
Register
0
29-23
Advertisement
Table of Contents
