Table of Contents
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A
A/D converter
bias, 27-37
block diagram, 27-35
channel decode, 27-36
comparator, 27-37
cycle times, 27-35
multiplexer, 27-36
operation, 27-34
sample buffer, 27-36
state machine, 27-37
successive approximation register (SAR), 27-37
Access error
on operand reads, 2-13
on operand writes, 2-14
Acknowledge error (ACKERR), 25-29
Address error exception, 2-14
Address variant, 29-4
Analog inputs, 27-73
Analog power signals, 27-63
Analog reference signals, 27-63
Analog supply
filtering, 27-67
grounding, 27-67
Async inputs signal timing, 33-22
Automatic echo, 23-25
B
Baud rate
calculating, 23-19
selection, 22-6
BDM
see debug
commands
DUMP, 29-27
FILL, 29-29
format, 29-21
GO, 29-31
NOP, 29-31
RAREG/RDREG, 29-23
RCREG, 29-32
RDMREG, 29-35
READ, 29-24
sequence diagrams, 29-22
summary, 29-20
WAREG/WDREG, 29-24
WCREG, 29-34
MOTOROLA
INDEX
WDMREG, 29-36
WRITE, 29-26
CPU halt, 29-16
operation with processor, 29-39
packet format
receive, 29-19
transmit, 29-19
recommended pinout, 29-46
register accesses
EMAC, 29-33
stack pointer, 29-33
serial interface, 29-18
timing diagrams
BDM serial port AC timing, 33-28
real-time trace AC timing, 33-28
Bit error (BITERR), 25-29
Bit reverse register (BITREV) instruction, 2-29
Bit stuff error (STUFFERR), 25-29
Branch instruction execution timing, 2-28
Buffer descriptors
receive (RxBD), 17-47
driver/DMA operation, 17-46
Bus
access by matches in CSCR and DACR, 13-4
characteristics, 13-2
data transfer
back-to-back cycles, 13-10
burst cycles, 13-10
cycle execution, 13-3
cycle states, 13-5
fast termination cycle, 13-9
read cycle, 13-6
write cycle, 13-8
electrical characteristics
input timing specifications, 33-10
output timing specifications, 33-11
features, 13-1
internal
arbitration, 8-9
MPARK, 8-12
MCF5282 User's Manual
allowable line access patterns, 13-11
line read bus cycles, 13-11
line transfers, 13-11
line write bus cycles, 13-13
algorithms, 8-11
fixed mode, 8-12
overview, 8-11
round-robin mode, 8-11
Index-1
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