Gpt Channel Interrupts (Cnf); Pulse Accumulator Overflow (Paovf); Pulse Accumulator Input (Paif); Timer Overflow (Tof) - Motorola ColdFire MCF5281 User Manual

Interrupts

20.8.1 GPT Channel Interrupts (CnF)

A channel flag is set when an input capture or output compare event occurs. Clear a channel
flag by writing a 1 to it.
When the fast flag clear all bit, GPTSCR1[TFFCA], is set, an
input capture read or an output compare write clears the
corresponding channel flag.
When a channel flag is set, it does not inhibit subsequent output
compares or input captures

20.8.2 Pulse Accumulator Overflow (PAOVF)

PAOVF is set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the
PAOVI bit in GPTPACTL is also set, PAOVF generates an interrupt request. Clear PAOVF
by writing a 1 to this flag.
When the fast flag clear all enable bit, GPTSCR1[TFFCA], is
set, any access to the pulse accumulator counter registers clears
all the flags in GPTPAFLG.

20.8.3 Pulse Accumulator Input (PAIF)

PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the
event edge sets PAIF. In gated time accumulation mode, the trailing edge of the gate signal
at the PAI pin sets PAIF. If the PAI bit in GPTPACTL is also set, PAIF generates an interrupt
request. Clear PAIF by writing a 1 to this flag.
When the fast flag clear all enable bit, GPTSCR1[TFFCA], is
set, any access to the pulse accumulator counter registers clears
all the flags in GPTPAFLG.

20.8.4 Timer Overflow (TOF)

TOF is set when the GPT counter rolls over from 0xFFFF to 0x0000. If the GPTSCR2[TOI]
bit is also set, TOF generates an interrupt request. Clear TOF by writing a 1 to this flag.
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MCF5282 User's Manual MOTOROLA