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Background Debug Mode (BDM)
29.5.3.3.2 Write A/D Register (
The operand longword data is written to the specified address or data register. A write alters
all 32 register bits. A bus error response is returned if the CPU core is not halted.
Command Format:
15
12
0x2
Command Sequence
WAREG/WDREG
???
Figure 29-20.
Operand Data
Result Data
29.5.3.3.3 Read Memory Location (
Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware
forces low-order address bits to zeros for word and longword accesses to ensure that word
addresses are word-aligned and longword addresses are longword-aligned.
29-24
WAREG
11
0x0
Figure 29-19.
WAREG
MS DATA
'NOT READY'
XXX
BERR
WAREG
Longword data is written into the specified address or data register.
The data is supplied most-significant word first.
Command complete status is indicated by returning 0xFFFF (with S
cleared) when the register write is complete.
READ
MCF5282 User's Manual
/
)
WDREG
8
7
0x8
D[31:16]
D[15:0]
/
Command Format
WDREG
LS DATA
'NOT READY'
NEXT CMD
'NOT READY'
/
Command Sequence
WDREG
)
4
3
2
A/D
Register
NEXT CMD
'CMD COMPLETE'
MOTOROLA
0
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