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Motorola MC68HC05T16 Technical Data Manual

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MC68HC05T16D/H
HC05
MC68HC05T16
MC68HC705T16
TECHNICAL
DATA
!MOTOROLA

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Summary of Contents for Motorola MC68HC05T16

  • Page 1 MC68HC05T16D/H HC05 MC68HC05T16 MC68HC705T16 TECHNICAL DATA !MOTOROLA...
  • Page 3 GENERAL DESCRIPTION PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMERS M-BUS SERIAL INTERFACE PULSE ACCUMULATOR PULSE WIDTH MODULATOR ON-SCREEN DISPLAY ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS...
  • Page 4 GENERAL DESCRIPTION PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMERS M-BUS SERIAL INTERFACE PULSE ACCUMULATOR PULSE WIDTH MODULATOR ON-SCREEN DISPLAY ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS...
  • Page 5 Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this Notice). A copy of Motorola’s Terms & Conditions of Supply is available on request.
  • Page 6 Conventions Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; shaded cells indicate that the bit is not described in the following paragraphs;...
  • Page 7 CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05T16D/H) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, if you prefer).
  • Page 8 14. We would be grateful if you would supply the following information (at your discretion), or attach your card. Name: Phone No: Position: FAX No: Department: Company: Address: Thank you for helping us improve our documentation, HKG CSIC Technical Publications , Motorola Semiconductors H.K. Ltd., Hong Kong. – Finally, tuck this edge into opposite flap –...

  • Page 9: Table Of Contents

    RESETS AND INTERRUPTS RESETS ........................4-1 4.1.1 Power-On Reset (POR)..................4-1 4.1.2 RESET Pin.......................4-1 4.1.3 Computer Operating Properly (COP) Reset ............4-2 INTERRUPTS......................4-4 4.2.1 Hardware Controlled Sequences ..............4-5 4.2.2 Software Interrupt (SWI) ..................4-6 4.2.3 External Interrupt (IRQ) ...................4-6 4.2.4 Programmable Timer Interrupt .................4-8 MC68HC05T16 MOTOROLA...
  • Page 10 6.3.2 M-Bus Clock Register (MCKR) ................6-6 6.3.3 M-Bus Control Register (MCR)................6-7 6.3.4 M-Bus Status Register (MSR) .................6-8 6.3.5 M-Bus Data I/O Register (MDR) ..............6-9 PULSE ACCUMULATOR Pulse Accumulator Registers ................7-1 7.1.1 PAC Control and Status Register (PACTL) ............7-1 MOTOROLA MC68HC05T16...
  • Page 11 Frame Control 3 and Status Register...............9-17 ANALOG TO DIGITAL CONVERTER 10.1 ADC Inputs ......................10-2 10.1.1 PF4/ADCIN1 ....................10-2 10.1.2 ADCIN0......................10-2 10.2 Program Example ....................10-2 10.3 ADC Control and Status Register ................10-3 CPU CORE AND INSTRUCTION SET 11.1 Registers ......................11-1 MC68HC05T16 MOTOROLA...
  • Page 12 OSD during Stop Mode..................12-2 12.1.6 ADC during Stop Mode..................12-2 12.1.7 COP during Stop Mode..................12-2 12.2 Wait Mode ......................12-3 OPERATING MODES 13.1 User Mode (Normal Operation) ................13-2 13.2 Self-Check Mode ....................13-2 13.3 Bootstrap Mode ....................13-4 13.3.1 EPROM Programming ...................13-4 MOTOROLA MC68HC05T16...
  • Page 13 14.1 Maximum Ratings ....................14-1 14.2 Thermal Characteristics..................14-1 14.3 DC Electrical Characteristics ................14-2 14.4 Open Drain Electrical Specification ..............14-3 14.5 On-Screen Display Timing ...................14-3 14.6 M-Bus Interface Timing .................14-4 14.7 Control Timing .....................14-5 MECHANICAL SPECIFICATIONS 15.1 56-pin SDIP Package...................15-1 MC68HC05T16 MOTOROLA...
  • Page 14 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA MC68HC05T16...
  • Page 15 LIST OF FIGURES Figure Page Number TITLE Number MC68HC05T16/MC68HC705T16 Block Diagram ..........1-2 Pin Assignments for 56-pin SDIP package.............2-3 Parallel Port I/O Circuitry ..................2-5 MC68HC05T16/MC68HC705T16 Memory Map ............3-2 Power-On Reset and RESET Timing..............4-3 Interrupt Stacking Order ..................4-4 External Interrupt Circuit and Timing ..............4-7 Programmable Timer Block Diagram..............5-2...
  • Page 16 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA MC68HC05T16 viii...
  • Page 17 Table Page Number TITLE Number I/O Pin Functions ....................2-4 MC68HC05T16/MC68HC705T16 Registers ............3-3 Reset Action on Internal Circuit ................4-2 Reset/Interrupt Vector Addresses ................4-5 COP Reset and RTI Rates ..................5-11 M-Bus Prescaler .....................6-6 RGB Color Map ......................9-7 Number of Visible Characters Per Row ..............9-14 11-1 MUL instruction.....................11-5...
  • Page 18 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA MC68HC05T16...

  • Page 19: General Description

    CPU, RAM, ROM, OSD, M-Bus, PWM, PAC, Timer, A/D converter, I/O and Watchdog Timer. The MC68HC705T16 is an EPROM version of the MC68HC05T16; it is available in windowed and OTP 56-pin SDIP packages. All references to the MC68HC05T16 apply equally to the MC68HC705T16, unless otherwise stated.
  • Page 20 SYSTEM TIMER PE4/PWM4* 7-BIT PE5/PWM5* EXTAL PE6/PWM6* ÷ 2 XTAL PE7/PWM7* ADCIN0 CHAR. CHAR. 5-BIT POWER PF0/PWM8* PF1/PWM9* PF2/I HFLBK PF3/HTONE MBUS PF4/ADCIN1 PF5/SDA PF6/SCL FBKG PF7/PACIN VFLBK *12V open-drain Figure 1-1 MC68HC05T16/ MC68HC705T16 Block Diagram MOTOROLA GENERAL DESCRIPTION MC68HC05T16...

  • Page 21: Pin Descriptions And Input/Output Ports

    PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS This section provides a description of the functional pins and I/O programming of the MC68HC05T16/ MC68HC705T16 microcontroller. PIN DESCRIPTIONS 56-pin SDIP PIN NAME DESCRIPTION PIN No. Power is supplied to the MCU using these two pins. VDD is power and...
  • Page 22 This OSD pin is the phase detector output pin. With a low-pass filter this pin controls the frequency of the internal OSD VCO. This is an input pin for biasing the internal OSD VCO. MOTOROLA PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS MC68HC05T16...
  • Page 23 PE2/PWM2 PE4/PWM4 PE1/PWM1 PE5/PWM5 PE0/PWM0 RESET PE6/PWM6 PE7/PWM7 XTAL PF0/PWM8 EXTAL PF1/PWM9 PF2/I PF3/HTONE PF4/ADCIN1 FBKG PF5/SDA VFLBK PF6/SCL HFLBK PF7/PACIN ADCIN0 TCAP IRQ/ VPP Figure 2-1 Pin Assignments for 56-pin SDIP package MC68HC05T16 PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS MOTOROLA...

  • Page 24: Input/Output Programming

    PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 0000 0000 State Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 on reset Port F Configuration Register ADC1 HTONE PWM9 PWM8 0000 0000 MOTOROLA PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS MC68HC05T16...
  • Page 25 DATA DIRECTION REGISTER TYPICAL PORT REGISTER I/O PORT LINES NOTE: (1) IP = INPUT PROTECTION PORT DATA (2) LATCH-UP PROTECTION NOT SHOWN & PORT DDR INTERNAL LOGIC Figure 2-2 Parallel Port I/O Circuitry MC68HC05T16 PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS MOTOROLA...
  • Page 26 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS MC68HC05T16...

  • Page 27: Memory And Registers

    I/O registers are memory-mapped so that the CPU can access their locations in the same way that it accesses all other memory locations. Figure 3-1 shows the Memory Map for the MC68HC05T16/ MC68HC705T16 . Input/Output Section The first 64 addresses of memory space, $0000-$003F, are the I/O section.
  • Page 28 $FFFE PWM9H Register M-Bus Address Register M-Bus Clock Register M-Bus Control Register M-Bus Status Register M-Bus Data Register ADC Control and Status Register ERPOM Programming Control Register Reserved Reserved Figure 3-1 MC68HC05T16/ MC68HC705T16 Memory Map MOTOROLA MEMORY AND REGISTERS MC68HC05T16...
  • Page 29 Table 3-1 MC68HC05T16/ MC68HC705T16 Registers Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port A data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1...
  • Page 30 Table 3-1 MC68HC05T16/ MC68HC705T16 Registers Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSD color palette 2 OSD color palette 3 OSD color palette 4 OSD row attribute MTRX3 MTRX2 MTRX1 MTRX0...

  • Page 31: Resets And Interrupts

    RESETS AND INTERRUPTS RESETS The MC68HC05T16 can be reset in three ways: by the initial power-on reset function, by an active low input to the RESET pin, and by a COP watchdog timer reset (if enabled). Any of these resets will cause the program to go to its starting address, specified by the contents of memory locations...

  • Page 32: Computer Operating Properly (Cop) Reset

    Clear all interrupt enable bits COP watchdog timer reset COP watchdog disabled Initialize M-Bus registers Initialize PWM registers Initialize PAC registers OSD disabled, all registers initialized to default values Listed numbers do not represent order of occurrence. MOTOROLA RESETS AND INTERRUPTS MC68HC05T16...
  • Page 33 2. Internal clock, internal address bus, and internal data bus signals are not available externally. 3. Next rising edge of internal clock after rising edge of RESET initiates reset sequence. Figure 4-1 Power-On Reset and RESET Timing MC68HC05T16 RESETS AND INTERRUPTS MOTOROLA...

  • Page 34: Interrupts

    INTERRUPTS The MC68HC05T16 is capable of handling eight types of interrupt, seven hardware and one software. The interrupt mask bit (“I” bit in the Condition Code register), if set, masks all interrupts except the software interrupt, SWI. Interrupts such as Timer, M-Bus, OSD, and MFT have several flags which will cause the interrupt.

  • Page 35: Hardware Controlled Sequences

    Timer and PAC clocks running. This “rest” state of the processor can be exited by RESET, an external interrupt (IRQ), or any of the interrupts described above. There are no special wait vectors for these individual interrupts. See section 12 on Low Power Modes. MC68HC05T16 RESETS AND INTERRUPTS MOTOROLA...

  • Page 36: Software Interrupt (Swi)

    The internal interrupt latch is cleared in the first part of the service routine; therefore, one (and only one) external interrupt pulse could be latched during t and serviced ILIL as soon as the I bit is cleared. MOTOROLA RESETS AND INTERRUPTS MC68HC05T16...
  • Page 37 Interrupt signals if after servicing an interrupt the external interrupt pins remain low, then the next interrupt is recognized. Normally used with wired connection. (b) Interrupt Mode Diagram Figure 4-3 External Interrupt Circuit and Timing MC68HC05T16 RESETS AND INTERRUPTS MOTOROLA...

  • Page 38: Programmable Timer Interrupt

    M-Bus interrupt is enabled when the M-Bus Interrupt Enable bit, MIEN of M-Bus Control register is set, provided the interrupt mask bit of the condition code register is cleared. There are three causes of M-Bus interrupt: MOTOROLA RESETS AND INTERRUPTS MC68HC05T16...
  • Page 39 The interrupt service routine address is specified by the contents of memory location $FFF4 and $FFF5. Reset disables the whole M-Bus block by clearing the M-Bus Control Register. Refer to Section 6 for detailed description of M-Bus. MC68HC05T16 RESETS AND INTERRUPTS MOTOROLA...

  • Page 40: Pac Interrupt

    Frame Control 3 and Status VFINTE MUTE1 MUTE0 VFLB R3CF R2CF R1CF R0CF 0000 0000 VFINTE - VFLBK interrupt enable 1 (set) – Vertical flyback interrupt enabled. 0 (clear) – Vertical flyback interrupt disabled. MOTOROLA RESETS AND INTERRUPTS MC68HC05T16 4-10...

  • Page 41: Multi-Function Timer Interrupts

    RTI circuit is E/16384 giving a maximum interrupt period of 3.9ms at a bus rate of 4.2MHz. A CPU interrupt request will be generated if RTIE is set. RTIE is cleared by writing a ‘0’ to the bit. MC68HC05T16 RESETS AND INTERRUPTS...
  • Page 42 RTIE - Real Time Interrupt Enable 1 (set) – Real time interrupt circuit is active. 0 (clear) – Real time interrupt circuit is inactive. Refer to section 5.2 for detailed description of Multi-Function Timer. MOTOROLA RESETS AND INTERRUPTS MC68HC05T16 4-12...

  • Page 43: Timers

    High byte - $16, Low byte - $17 – Counter Register High byte - $18, Low byte - $19 – Alternate Counter Register High byte - $1A, Low byte - $1B A description of each register is provided in the following paragraphs. MC68HC05T16 TIMERS MOTOROLA...
  • Page 44 MC68HC05T16 INTERNAL BUS INTERNAL 8 BIT PROCESSOR BUFFER CLOCK ÷ 4 OUTPUT OUTPUT 16 BIT FREE INPUT COMPARE COMPARE RUNNING CAPTURE REGISTER 1 REGISTER 2 COUNTER REGISTER COUNTER ALTERNATE REGISTER OUTPUT OUTPUT OVERFLOW EDGE COMPARE COMPARE DETECT DETECT CIRCUIT 1...

  • Page 45: Counter

    High byte - $16, Low byte - $17 Each 16-bit Output Compare register is made up of two 8-bit registers. These Output Compare registers are used for several purposes, such as indicating when a period of time has elapsed. All MC68HC05T16 TIMERS MOTOROLA...

  • Page 46: Input Capture Registers

    Resolution is one count of the free-running counter, which is four internal bus clock cycles. The free-running counter contents are transferred to the input capture register on each valid signal transition whether the input capture flag (ICF) is set or clear. The input capture register always MOTOROLA TIMERS MC68HC05T16...

  • Page 47: Timer Control Register (Tcr)

    TOVFIE - Timer Overflow Interrupt Enable 1 (set) – Timer Overflow interrupt enabled. 0 (clear) – Timer Overflow interrupt disabled. IEDG - Input Edge 1 (set) – TCAP is positive-going edge sensitive. 0 (clear) – TCAP is negative-going edge sensitive. MC68HC05T16 TIMERS MOTOROLA...

  • Page 48: Timer Status Register (Tsr)

    OC0F will be set when its output compare 1 register contents match that of the free-running counter; an output compare interrupt will be generated, if OC1IE is set. OC1F is cleared by reading the TSR and then the Output Compare 1 Low register ($17). MOTOROLA TIMERS MC68HC05T16...

  • Page 49: Programmable Timer Timing Diagrams

    The relationships between the internal clock signals, the counter contents and the status of the flag bits are shown in the following diagrams. It should be noted that the signals labelled ‘internal’ (processor clock, timer clocks and Reset) are not available to the user. MC68HC05T16 TIMERS MOTOROLA...
  • Page 50 If the input edge occurs in the shaded area from one timer state T10 to the other timer state T10 the input capture flag is set during the next state T11. Figure 5-3 Timer State Timing Diagram for Input Capture MOTOROLA TIMERS MC68HC05T16...
  • Page 51 The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by a read of the timer status register during the internal processor clock high time followed by a read of the counter low register. Figure 5-5 Timer State Diagram for Timer Overflow MC68HC05T16 TIMERS MOTOROLA...

  • Page 52: Multi-Function Timer

    RTIE IRQN WDOG 0000 0011 The MFT provides miscellaneous function to the MC68HC05T16 MCU. It includes a timer overflow function, real-time interrupt, and COP watchdog. The external interrupt (IRQ) triggering option is also set by this Multi-Function Timer register. The clock base for this module is derived from the bus clock divided by four. For a 4.2MHz E (CPU) clock, the clock base is 1.05 MHz.

  • Page 53: Cop Watchdog Reset

    Minimum COP reset period RTI period E clock = 4.2MHz E clock = 4.2MHz 27.3ms 3.9ms 54.6ms 7.8ms 109.27ms 15.6ms 218.4ms 31.2ms RT0 and RT1 should only be changed immediately after COP watchdog timer has been reset. MC68HC05T16 TIMERS MOTOROLA 5-11...
  • Page 54 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA TIMERS MC68HC05T16 5-12...

  • Page 55: M-Bus Serial Interface

    M-BUS SERIAL INTERFACE M-Bus (Motorola Bus) is a two-wire, bidirectional serial bus which provides a simple, efficient way for data exchange between devices. It is fully compatible with the I C bus standard. This two-wire bus minimizes the interconnection between devices and eliminates the need for address decoders;...

  • Page 56: M-Bus Protocol

    Normally, a standard communication is composed of four parts, 1) START signal, 2) slave address transmission, 3) data transfer, and 4) STOP signal. They are described briefly in the following sections and illustrated in Figure 6-2. MOTOROLA M-BUS SERIAL INTERFACE MC68HC05T16...

  • Page 57: Start Signal

    Only the slave with matched address will respond by sending back an acknowledge bit by pulling the SDA low at the 9th clock; see Figure 6-2. MC68HC05T16 M-BUS SERIAL INTERFACE MOTOROLA...

  • Page 58: Data Transfer

    The transition from master to slave mode will not generate a STOP condition. Meanwhile, a software bit will be set by hardware to indicate loss of arbitration. MOTOROLA M-BUS SERIAL INTERFACE MC68HC05T16...

  • Page 59: Clock Synchronization

    SCL line. M-Bus Registers There are five registers used in the M-Bus interface, these are discussed in the following paragraphs. MC68HC05T16 M-BUS SERIAL INTERFACE MOTOROLA...

  • Page 60: M-Bus Address Register (Madr)

    MBC2 MBC1 MBC0 DIVIDER 1088 1408 1536 1792 2176 2816 3072 3584 4352 For a 4.2MHz external crystal operation (2.1MHz internal operating frequency), the serial bit clock frequency of M-Bus ranges from 483Hz to 95,455Hz. MOTOROLA M-BUS SERIAL INTERFACE MC68HC05T16...

  • Page 61: M-Bus Control Register (Mcr)

    If cleared, an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data. If set, no acknowledge signal response. This is an active low control bit. MC68HC05T16 M-BUS SERIAL INTERFACE...

  • Page 62: M-Bus Status Register (Msr)

    This arbitration lost flag is set when the M-bus master loses arbitration during a master transmission mode. When ALOST is set, the MIF (M-bus interrupt) bit is also set. This bit must be cleared by software. MOTOROLA M-BUS SERIAL INTERFACE MC68HC05T16...

  • Page 63: M-Bus Data I/O Register (Mdr)

    In master transmit mode, data written into this register is sent to the bus automatically, with the most significant bit out first. In master receive mode, reading of this register initiates receiving of the next byte data. In slave mode, the same function applies after it has been addressed. MC68HC05T16 M-BUS SERIAL INTERFACE MOTOROLA...
  • Page 64 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA M-BUS SERIAL INTERFACE MC68HC05T16 6-10...

  • Page 65: Pulse Accumulator

    It is set when the count in the pulse accumulator rolls over from $FF to $00. PAOF is cleared by writing a “0” to the bit. An interrupt to the CPU is generated if the PAIE bit is set. MC68HC05T16 PULSE ACCUMULATOR...

  • Page 66: Pac Counter Register

    When PAC is disabled (PAEN=0), the counter will be cleared to zero. This ensures the Counter starts from zero every time it is disabled and enabled. The Pulse Accumulator Counter is read only and resets to zero a write operation. MOTOROLA PULSE ACCUMULATOR MC68HC05T16...

  • Page 67: Pulse Width Modulator

    PULSE WIDTH MODULATOR The MC68HC05T16 has 10 PWM channels, with output pins shared with port E and port F pins. Nine 7-bit channels are driven by the Timer clock, the other single 14-bit channel is driven by the CPU clock. All PWM outputs are +12V open-drain type; therefore a pull-up resistor is required at each PWM pin.

  • Page 68: 14-Bit Pwm Channel

    The 8-bit register works in the same way as the 7-bit PWMs. That is, the value set in this 8-bit register determines the basic duty cycle of the waveform. A value of $00 results in a continuously MOTOROLA PULSE WIDTH MODULATOR MC68HC05T16...
  • Page 69 4, 12, 20, 28, 36, 44, 52, 60 --x1xxxx 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 --1xxxxx 1, 3, 5, 7, ..61, 63 Figure 8-2 14-Bit PWM Output Waveform MC68HC05T16 PULSE WIDTH MODULATOR MOTOROLA...
  • Page 70 The instruction STA $35 simply puts the 6-bit BRM data in a buffer. Output is not affected at this time. The instruction STA $36, then, puts the total 14-bit data to BRM and PWM register at the same time. Output waveform will change accordingly starting from the beginning of the next PWM cycle. MOTOROLA PULSE WIDTH MODULATOR MC68HC05T16...

  • Page 71: On-Screen Display

    Background and blinking features are on per character basis; whereas bordering feature is on per row basis. Users have to be careful while designing their character fonts so that bordering effect is not nullified between adjacent characters in the same row or in two consecutive rows. MC68HC05T16 ON-SCREEN DISPLAY MOTOROLA...

  • Page 72: Features

    Row character black-edge features: bordering or shadowing • Double scan mode support for non-interlaced scan TV system • Half tone capability for creating transparent background effect • Video mute. Three color selections for video mute: black, green, and blue MOTOROLA ON-SCREEN DISPLAY MC68HC05T16...

  • Page 73: Characters

    Character ROM/EPROM is not readable to the CPU in user mode. OSD character ROM is located from $8000 to $8FFF. Three characters in the Character ROM are fixed, and cannot be changed. They are shown in Figure 9-2. MC68HC05T16 ON-SCREEN DISPLAY MOTOROLA...
  • Page 74 ROW BUFFER 3 $2C1 $2F1 $2FF Last 8 character register pairs of a row buffer are not used when that row buffer is configured for displaying 16x16 dot characters Figure 9-1 OSD Character and Row Structure MOTOROLA ON-SCREEN DISPLAY MC68HC05T16...

  • Page 75: Character Registers

    CH6-CH0 is mapped to the 16 RAM codes. 0 (clear) – CH6-CH0 is mapped to the 128 ROM/EPROM codes. CH6-CH0 0 to 127 = ROM/EPROM codes. 0 to 15 = RAM codes. Codes 16 and higher are invalid. MC68HC05T16 ON-SCREEN DISPLAY MOTOROLA...

  • Page 76: Color Palette Registers

    Table 9-1 shows the RGB color map. Palette 0 Palette 1 Palette 2 Palette 3 Palette 4 Palette 5 Palette 6 Palette 7 Color selected using Ii, Ri, Gi, and Bi 16 available colors Figure 9-3 Color Palette Organization MOTOROLA ON-SCREEN DISPLAY MC68HC05T16...

  • Page 77: Row

    16x16 character dot matrix selected for row i. If 12x16 matrix is selected, a maximum of 32 characters may be displayed for that row. Rows selected for 16x16 matrix characters, the maximum is 24 characters per row; the remaining 8 MC68HC05T16 ON-SCREEN DISPLAY MOTOROLA...

  • Page 78: Row Vertical Position Registers

    FBKG output pin is active only where character dots exist in the character dot matrix (including bordering or shadowing dots). The FBKG and HTONE pins may be used to create transparent background effects for OSD displays. MOTOROLA ON-SCREEN DISPLAY MC68HC05T16...
  • Page 79 After the first four lines of row (i+1) have been displayed, row i display will commence and continue for the next sixteen lines, blocking off row (i+1) display for these sixteen lines. After row i display has been terminated, there are still (64-4-16)=44 lines of row (i+1) display MC68HC05T16 ON-SCREEN DISPLAY MOTOROLA...
  • Page 80 Note that the judgement of overlap is totally based on the vertical position of rows, it has nothing to do with character size of rows. RiCF bit of Frame Control 3 and Status register will also be set when a row display is terminated. MOTOROLA ON-SCREEN DISPLAY MC68HC05T16 9-10...
  • Page 81 Figure 9-5 Output Signal Timing Diagram - With Background Row (i+1) Row (i+1) partially overlaps row i Row i Row (j+1) Row (j+1) and row j completely overlaps, therefore only row j is visible Row j Figure 9-6 Resolution of Overlap among Rows MC68HC05T16 ON-SCREEN DISPLAY MOTOROLA 9-11...

  • Page 82: Row Horizontal Position Register

    Note that for the case where row i is completely overlapped by other rows, row i display has never really happened, that is, terminated upon its commencement, row i interrupt will never occur. MOTOROLA ON-SCREEN DISPLAY MC68HC05T16 9-12...

  • Page 83: Row Control Register 2

    Users can avoid filling the unused bytes in a row since these bytes will not be displayed. Table 9-2 lists the number of valid character bytes per row. Frame The following registers affect the frame of an OSD displays. MC68HC05T16 ON-SCREEN DISPLAY MOTOROLA 9-13...

  • Page 84: Frame Control 1 And Row Count Register

    FADE bit is set, frame display will gradually appear (fade in) if ON/OFF is set, and gradually disappear (fade out) if ON/OFF is clear. If FADE bit is clear, OSD display will be turned on or off instantly. MOTOROLA ON-SCREEN DISPLAY MC68HC05T16 9-14...
  • Page 85 These bits control the blinking rate of all symbols on the TV screen. The on/off ratio of blinking is always 3/1. VFPOL - VFLBK input polarity select 1 (set) – Vertical flyback signal at VFLBK is active low. 0 (clear) – Vertical flyback signal at VFLBK is active high. MC68HC05T16 ON-SCREEN DISPLAY MOTOROLA 9-15...
  • Page 86 Before fading out 1st step: 8 lines off 2nd step: 12 lines off 3rd step: 14 lines off 4th step: 15 lines off Last step: all 16 lines off Figure 9-7 Fading Out Sequence MOTOROLA ON-SCREEN DISPLAY MC68HC05T16 9-16...

  • Page 87: Frame Control 3 And Status Register

    Bits 7 to 5 are control bits whereas bits 4 to 0 are status bits associated with interrupt. A status bit is cleared by writing a 0 to that bit. Care must be taken while clearing a status bit: make sure the MC68HC05T16 ON-SCREEN DISPLAY...
  • Page 88 Row i display has been terminated. 0 (clear) – Row i display has been not terminated. Whenever a row display has been terminated, the corresponding RiCF flag will be set along with update of CDRC3-CDRC0 field. MOTOROLA ON-SCREEN DISPLAY MC68HC05T16 9-18...

  • Page 89: Analog To Digital Converter

    ADC Control/Status register to all 1’s. This disable function is mainly for low power applications. Figure 10-1 shows a block diagram of the ADC module. RESULT – ADCIN0 or ADCIN1 Figure 10-1 ADC Block Diagram MC68HC05T16 ANALOG TO DIGITAL CONVERTER MOTOROLA 10-1...

  • Page 90: Adc Inputs

    #$00 to #$20. ADCSR is the ADC Control/Status register. #$00 ADCSR ;ADC Control and Status Register BRSET 7, ADCSR, ATD ADCSR ADCSR #$1F #$1F ;out of range ;analog value in ADC. ;ANALOG IN = ([AD4:0] +1)*0.15625V at Vdd = 5V MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC05T16 10-2...

  • Page 91: Adc Control And Status Register

    RESULT bit to change state from the value immediately before or after it, AD4-0 are considered to be the digital equivalent of the analog input. Note that when AD4-0 are all 1’s, ADC is virtually turned off to minimize power consumption. MC68HC05T16 ANALOG TO DIGITAL CONVERTER MOTOROLA...
  • Page 92 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC05T16 10-4...

  • Page 93: Cpu Core And Instruction Set

    Negative Interrupt mask Half carry Figure 11-1 Programming model 11.1.1 Accumulator (A) The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. MC68HC05L1 CPU CORE AND INSTRUCTION SET MOTOROLA 11-1...

  • Page 94: Index Register (X)

    Each bit is explained in the following paragraphs. Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. MOTOROLA CPU CORE AND INSTRUCTION SET MC68HC05L1 11-2...

  • Page 95: Instruction Set

    (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 11-1. MC68HC05L1 CPU CORE AND INSTRUCTION SET MOTOROLA 11-3...

  • Page 96: Register/Memory Instructions

    Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 11-7), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 11-8). MOTOROLA CPU CORE AND INSTRUCTION SET MC68HC05L1...
  • Page 97 AND memory with A OR memory with A Exclusive OR memory with A Arithmetic compare A with memory Arithmetic compare X with memory Bit test memory with A (logical compare) Jump unconditional Jump to subroutine MC68HC05L1 CPU CORE AND INSTRUCTION SET MOTOROLA 11-5...
  • Page 98 Branch if bit n is set BRSET n (n=0–7) 2•n Branch if bit n is clear BRCLR n (n=0–7) 01+2•n Set bit n BSET n (n=0–7) 10+2•n Clear bit n BCLR n (n=0–7) 11+2•n MOTOROLA CPU CORE AND INSTRUCTION SET MC68HC05L1 11-6...
  • Page 99 Transfer X to A Set carry bit Clear carry bit Set interrupt mask bit Clear interrupt mask bit Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-operation Stop STOP Wait WAIT MC68HC05L1 CPU CORE AND INSTRUCTION SET MOTOROLA 11-7...
  • Page 100 Indexed (no offset) Interrupt mask • Not affected Direct Indexed, 1 byte offset Negate (sign bit) Load CCR from stack EXT Extended Indexed, 2 byte offset Zero Cleared Inherent Relative Carry/borrow Not implemented MOTOROLA CPU CORE AND INSTRUCTION SET MC68HC05L1 11-8...
  • Page 101 Indexed (no offset) Interrupt mask • Not affected Direct Indexed, 1 byte offset Negate (sign bit) Load CCR from stack EXT Extended Indexed, 2 byte offset Zero Cleared Inherent Relative Carry/borrow Not implemented MC68HC05L1 CPU CORE AND INSTRUCTION SET MOTOROLA 11-9...
  • Page 102 Table 11-8 M68HC05 opcode map MOTOROLA CPU CORE AND INSTRUCTION SET MC68HC05L1 11-10...

  • Page 103: Addressing Modes

    Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. EA = (PC+1); PC ← PC+2 Address bus high ← 0; Address bus low ← (PC+1) MC68HC05L1 CPU CORE AND INSTRUCTION SET MOTOROLA 11-11...

  • Page 104: Extended

    8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing.

  • Page 105: Relative

    –126 to +129 from the opcode address. The programmer need not calculate the offset when using the Motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch.
  • Page 106 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA CPU CORE AND INSTRUCTION SET MC68HC05L1 11-14...

  • Page 107: Low Power Modes

    (and data) from that first valid edge which occurred during the Stop mode. Notice that an exit by a reset will reset the entire MCU and thus, this function on the TCAP will not happen. MC68HC05T16 LOW POWER MODES MOTOROLA...

  • Page 108: M-Bus During Stop Mode

    IRQ. If exit from Stop mode was caused by a reset, the MCU will be initialized and the COP watchdog system will be disabled. MOTOROLA LOW POWER MODES MC68HC05T16 12-2...

  • Page 109: Wait Mode

    Wait mode is performed (e.g. timer overflow interrupt exit), the state of the remaining systems will be unchanged. If a reset exit from the Wait mode is performed, all the systems revert to the default reset state. MC68HC05T16 LOW POWER MODES MOTOROLA...
  • Page 110 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA LOW POWER MODES MC68HC05T16 12-4...

  • Page 111: Operating Modes

    OPERATING MODES The MC68HC05T16/ MC68HC705T16 MCU has two modes of operation, the User Mode and the Self-Check/ Bootstrap Mode. Figure 13-1 shows the flowchart of entry to these two modes, and Table 13-1 shows operating mode selection. RESET USER MODE...

  • Page 112: User Mode (Normal Operation)

    13.2 Self-Check Mode The MC68HC05T16 self-check mode is for the user to check device functions with an on-chip self-check program masked at location $FE00 to $FFEF under minimum hardware support. The hardware is shown in Figure 13-3. Figure 13-2 is the criteria to enter self-check mode, where PC2’s condition is latched within first two clock cycles after the rising edge of the reset.
  • Page 113 MC68HC05T16 470K 0.1µ 8 x 4K7 VFLBK HFLBK 0.1µ PE0/PWM0 PE1/PWM1 PE2/PWM2 FBKG PE3/PWM3 IRQ/VPP PE4/PWM4 PE5/PWM5 PE6/PWM6 2N4400 PE7/PWM7 PF0PWM8 PF1/PWM9 PF2/I PF3/HTONE PF4/ADCIN1 PF5/SDA PF6/SCL PF7PACIN TCAP ADCIN0 Figure 13-3 MC68HC05T16 Self-Test Circuit MC68HC05T16 OPERATING MODES MOTOROLA 13-3...

  • Page 114: Bootstrap Mode

    The 4K-bytes OSD CHAR EPROM is positioned from $8000 to $8FFF, and the 23.5K-bytes user EPROM is positioned from $A000 to $FDFF. The erased state of EPROM locations is $FF. Programming boards are available from Motorola for programming the on-chip EPROM, please contact your Motorola representative.

  • Page 115: Eprom Programming Sequence

    ;load data=00 in to A $B000,X ;latch data and address (if programming OSD CHAR ;EPROM, the address should be in the range of ;$8000 to $8FFF) BSET 0,PCR ;program DELAY ;call delay subroutine for 1ms ;reset PCR MC68HC05T16 OPERATING MODES MOTOROLA 13-5...
  • Page 116 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA OPERATING MODES MC68HC05T16 13-6...

  • Page 117: Maximum Ratings

    UNIT Supply Voltage –0.3 to +7.0 Input Voltage –0.3 to V +0.3 Input Voltage at Open Drain pins inod IRQ (MC68HC05T16) –0.3 to 10 (MC68HC705T16) –0.3 to 12+0.5 Current Drain per pin excluding V and V °C Operating Temperature 0 to 70 °C...

  • Page 118: Dc Electrical Characteristics

    (4.2MHz oscillator off) – I/O ports high-Z leakage current ±10 µA PA0-PA7, PB0-PB7, PC0-PC7, – – PE0-PE7, PF0-PF7 Input current ±1 µA TCAP, IRQ, RESET, EXTAL, ADCIN0, – – HFLBK, VFLBK Capacitance All signal pins MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC05T16 14-2...

  • Page 119: Open Drain Electrical Specification

    Fall Time (I =2K, 12pF; 0.9 to 0.1V LOAD – – R, G, B, FBKG, HTONE, I Dot clock frequency – 16.128 – HFLBK rise time – – VFLBK rise time – – ripple – – MC68HC05T16 ELECTRICAL SPECIFICATIONS MOTOROLA 14-3...

  • Page 120: M-Bus Interface Timing

    SDA data setup time – SU.DAT SDA data hold time – HD.DAT STOP condition setup time – SU.STO Note: 1. With 200pF loading on the SDA/SCL pins HD.STA HIGH SU.DAT HD.DAT SU.STA SU.STO Figure 14-1 M-Bus Timing Diagram MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC05T16 14-4...

  • Page 121: Control Timing

    , the low TCAP pulse width applies. 3. The minimum period t should not be less than the number of cycle times it takes to execute TLTL the input capture interrupt service routine plus 24t MC68HC05T16 ELECTRICAL SPECIFICATIONS MOTOROLA 14-5...
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  • Page 123: Mechanical Specifications

    MECHANICAL SPECIFICATIONS This section provides the mechanical dimension for the 56-pin SDIP package for the MC68HC05T16. 15.1 56-pin SDIP Package - A - Case No. 859-01 - B - 56 lead SDIP 0.25 M T B S - T -...
  • Page 124 THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA MECHANICAL SPECIFICATIONS MC68HC05T16 15-2...
  • Page 125 GENERAL DESCRIPTION PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMERS M-BUS SERIAL INTERFACE PULSE ACCUMULATOR PULSE WIDTH MODULATOR ON-SCREEN DISPLAY ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS...
  • Page 126 GENERAL DESCRIPTION PIN DESCRIPTIONS AND INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS TIMERS M-BUS SERIAL INTERFACE PULSE ACCUMULATOR PULSE WIDTH MODULATOR ON-SCREEN DISPLAY ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS...
  • Page 128 USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 !MOTOROLA...

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