Sram Base Address Register (Rambar) - Motorola ColdFire MCF5281 User Manual

SRAM Programming Model
5.3.1

SRAM Base Address Register (RAMBAR)

The configuration information in the SRAM base address register (RAMBAR) controls the
operation of the SRAM module.
• The RAMBAR holds the base address of the SRAM. The MOVEC instruction
provides write-only access to this register.
• The RAMBAR can be read or written from the debug module in a similar manner.
• All undefined bits in the register are reserved. These bits are ignored during writes
to the RAMBAR, and return zeroes when read from the debug module.
• The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other
bits are unaffected.
The RAMBAR contains several control fields. These fields are shown in Figure 5-1
31 30
Field BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16
Reset
R/W
15 14
Field —
Reset
R/W
Address
Figure 5-1. SRAM Base Address Register (RAMBAR)
Bits Name
31–16 BA
15–12 —
11–10 PRI1, PRI2
5-2
29 28 27 26 25
13 12 11 10
PRI1 PRI2 SPV
Table 5-1. SRAM Base Address Register
Base address. Defines the 0-modulo-64K base address of the SRAM module. By
programming this field, the SRAM may be located on any 64-Kbyte boundary within the
processor's 4-Gbyte address space.
Reserved, should be cleared.
Priority bit. PRI1 determines if DMA or CPU has priority in upper 32k bank of memory. PRI2
determines if DMA or CPU has priority in lower 32k bank of memory. If bit is set, DMA has
priority. If bit is reset, CPU has priority. Priority is determined according to the following
table.
PRI[1:2]
00
01
10
11
NOTE: The Motorola-recommended setting for the priority bits is 00.
MCF5282 User's Manual
24 23 22 21
Undefined
W
9 8 7 6 5
WP — C/I
Undefined
W
CPU + 0xC05
Description
Upper Bank
Priority
DMA Accesses
DMA Accesses
CPU Accesses
CPU Accesses
20 19 18 17
4 3 2 1
SC SD UC UD
Lower Bank
Priority
DMA Accesses
CPU Accesses
DMA Accesses
CPU Accesses
MOTOROLA
16
0
V
0