Cache Operation; Interaction With Other Modules; Cache Block Diagram - Motorola ColdFire MCF5281 User Manual

Local Address Bus
31
10
4.3

Cache Operation

The cache is physically connected to the ColdFire core's local bus, allowing it to service all
fetches from the ColdFire core and certain memory fetches initiated by the debug module.
Typically, the debug module's memory references appear as supervisor data accesses but
the unit can be programmed to generate user-mode accesses and/or instruction fetches. The
cache processes any fetch access in the normal manner.
4.3.1

Interaction with Other Modules

Because both the cache and high-speed SRAM module are connected to the ColdFire core's
local data bus, certain user-defined configurations can result in simultaneous fetch
processing.
If the referenced address is mapped into the SRAM module, that module will service the
request in a single cycle. In this case, data accessed from the cache is simply discarded and
no external memory references are generated. If the address is not mapped into the SRAM
space, the cache handles the request in the normal fashion.
MOTOROLA
31
4 3 1 2 0
I or D Line
=
Fill Hit
31
TAG
Tag Hit
Figure 4-1. Cache Block Diagram
Chapter 4. Cache
External Data[31:0]
4
I or D Line Buffer Storage
Buffer
Address
11
0
128
=
Cache Operation
MUX
31 0
0
DATA
'512
MUX
Local Data Bus
4-3