Low-Power Control Register (Lpcr); Xlpm_Ipl Settings; Lpcr Field Descriptions - Motorola ColdFire MCF5281 User Manual

Memory Map and Registers
XLPM_IPL [2:0]
000
001
010
011
100
101
11x
7.2.3.2

Low-Power Control Register (LPCR)

The LPCR controls chip operation and module operation during low-power modes.
Field
Reset
R/W
Address
Bits Name
7–6 LPMD
5 —
4–3 STPMD
2 —
1 LVDSE
0 —
7-4
Table 7-3. XLPM_IPL Settings
Interrupts Level Needed to Exit Low-Power Mode
Any interrupt request exits low-power mode
Interrupt request levels [2-7] exit low-power mode
Interrupt request levels [3-7] exit low-power mode
Interrupt request levels [4-7] exit low-power mode
Interrupt request levels [5-7] exit low-power mode
Interrupt request levels [6-7] exit low-power mode
Interrupt request level [7] exits low-power mode
7 6 5
LPMD —
IPSBAR + 0x0011_0007
Figure 7-2. Low-Power Control Register (LPCR)
Table 7-4. LPCR Field Descriptions
Low-power mode select. Used to select the low-power mode the chip enters once
the ColdFire CPU executes the STOP instruction. These bits must be written prior
to instruction execution for them to take effect. The LPMD[1:0] bits are readable
and writable in all modes. Table 7-5 illustrates the four different power modes that
can be configured with the LPMD bit field.
Reserved, should be cleared.
PLL/CLKOUT stop mode. Controls PLL and CLKOUT operation in stop mode as
shown in Table 7-6
Reserved, should be cleared.
LDV standby enable. Controls whether the PMM enters VREG Standby Mode
(LVD disabled) or VREG Pseudo-Standby (LVD enabled) mode when the PMM
receives a power down request. This bit has no effect if the RCR[LVDE] bit is a
logic 0.
1 VREG Pseudo-Standby mode (LVD enabled on power down request).
0 VREG Standby mode (LVD disabled on power down request).
Reserved, should be cleared.
MCF5282 User's Manual
4 3 2
STPMD — LVDSE
0000_0010
R/W
Description
1 0
—
MOTOROLA