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Figure
Number
7-1
Low-Power Interrupt Control Register (LPICR) ......................................................... 7-3
7-2
Low-Power Control Register (LPCR) ......................................................................... 7-4
8-1
IPS Base Address Register (IPSBAR).......................................................................... 8-4
8-2
Memory Base Address Register (RAMBAR) .............................................................. 8-5
8-3
Core Reset Status Register (CRSR)............................................................................. 8-6
8-4
Core Watchdog Control Register (CWCR) ................................................................. 8-8
8-5
Core Watchdog Service Register (CWSR) .................................................................. 8-9
8-6
Arbiter Module Functions........................................................................................... 8-10
8-7
Default Bus Master Park Register (MPARK)............................................................. 8-12
8-8
Master Privilege Register (MPR) .............................................................................. 8-16
8-9
Peripheral Access Control Register (PACRn) ............................................................ 8-17
8-10
GPACR Register......................................................................................................... 8-18
9-1
Clock Module Block Diagram ...................................................................................... 9-3
9-2
PLL Block Diagram...................................................................................................... 9-4
9-3
Synthesizer Control Register (SYNCR) ....................................................................... 9-6
9-4
Synthesizer Status Register (SYNSR) .......................................................................... 9-8
9-5
Crystal Oscillator Example ......................................................................................... 9-12
9-6
Lock Detect Sequence ................................................................................................ 9-15
10-1
Interrupt Pending Register High (IPRHn) .................................................................. 10-7
10-2
Interrupt Pending Register Low (IPRLn) ................................................................... 10-7
10-3
Interrupt Mask Register High (IMRHn) ..................................................................... 10-8
10-4
Interrupt Mask Register Low (IMRLn) ...................................................................... 10-8
10-5
Interrupt Force Register High (INTFRCHn) .............................................................. 10-9
10-6
Interrupt Force Register Low (INTFRCLn) ............................................................. 10-10
10-7
Interrupt RequestLevel Register (IRLRn) ................................................................ 10-10
10-8
IACK Level and Priority Register (IACKLPRn) ..................................................... 10-11
10-9
Interrupt Control Register (ICRnx)........................................................................... 10-12
10-10
Software and Level n IACK Registers (SWIACKR, L1IACK-L7IACK) ............... 10-16
11-1
EPORT Block Diagram .............................................................................................. 11-1
11-2
EPORT Pin Assignment Register (EPPAR) ............................................................... 11-4
11-3
EPORT Data Direction Register (EPDDR) ................................................................ 11-4
11-4
EPORT Port Interrupt Enable Register (EPIER) ........................................................ 11-5
11-5
EPORT Port Data Register (EPDR) ........................................................................... 11-5
11-6
EPORT Port Pin Data Register (EPPDR)................................................................... 11-6
11-7
EPORT Port Flag Register (EPFR) ............................................................................ 11-6
12-1
Connections for External Memory Port Sizes ............................................................ 12-4
12-2
Chip Select Address Registers (CSARn)................................................................... 12-6
12-3
Chip Select Mask Registers (CSMRn) ...................................................................... 12-7
12-4
Chip Select Control Registers (CSCRn) ..................................................................... 12-8
13-1
Signal Relationship to CLKOUT for Non-DRAM Access ........................................ 13-2
13-2
Connections for External Memory Port Sizes ............................................................ 13-3
13-3
Chip-Select Module Output Timing Diagram ............................................................ 13-3
xxiv
ILLUSTRATIONS
Title
MCF5282 User's Manual
Page
Number
MOTOROLA
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