Sdram Read Cycle; Sdram Timing - Motorola ColdFire MCF5281 User Manual

Processor Bus Output Timing Specifications
Figure 33-5 shows an SDRAM read cycle.
CLKOUT
D1
A[23:0]
SRAS
1
SCAS
DRAMW
D[31:0]
SDRAM_CS[1:0]
BS[3:0]
NUM
D1 CLKOUT high to SDRAM address valid
D2
D3 CLKOUT high to SDRAM address invalid
D4 CLKOUT high to SDRAM control invalid
D5
D6
2
D7
2
D8
1
All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2
D7 and D8 are for write cycles only.
33-16
0 1 2 3
D3
Row
D4
D2
ACTV NOP
1
DACR[CASL] = 2
Figure 33-5. SDRAM Read Cycle
Table 33-12. SDRAM Timing
1
Characteristic
CLKOUT high to SDRAM control valid
SDRAM data valid to CLKOUT high
CLKOUT high to SDRAM data invalid
CLKOUT high to SDRAM data valid
CLKOUT high to SDRAM data invalid
MCF5282 User's Manual
4 5 6 7 8
Column
D4
NOP
READ
9 10 11 12
D5
D6
D4
PRE
Symbol Min
t —
CHDAV
t —
CHDCV
t 2
CHDAI
t 2
CHDCI
t 6
DDVCH
t 1
CHDDI
t —
CHDDVW
t 2
CHDDIW
MOTOROLA
13
Max Unit
10 ns
10 ns
— ns
— ns
— ns
— ns
10 ns
— ns