Page 1 MPC860 Overview Memory Map Hardware Interface Overview PowerPC Core Overview PowerPC Core Register Set MPC860 Instruction Set PowerPC Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing System Interface Unit Reset External Signals MPC860 External Bus Interface Clocks and Power Control Memory Controller PCMCIA Interface Communications Processor Module and CPM Timers...
Page 2 MPC860 Overview Memory Map Hardware Interface Overview PowerPC Core Overview PowerPC Core Register Set MPC860 Instruction Set PowerPC Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing System Interface Unit Reset External Signals MPC860 External Bus Interface Clocks and Power Control Memory Controller PCMCIA Interface Communications Processor Module and CPM Timers...
Page 3 MPC860UM/AD 07/98 REV. 1 ª MPC860 PowerQUICC UserÕs Manual...
Page 4 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and speciÞcally disclaims any and all liability, including without limitation consequential or incidental damages.
Page 5: Table Of Contents
Embedded PowerPC Core..................1-6 System Interface Unit (SIU).................1-7 PCMCIA Controller .....................1-7 Power Management....................1-7 Communications Processor Module (CPM) ............1-8 Software Compatibility Issues ................1-9 Chapter 2 Memory Map Chapter 3 Hardware Interface Overview System Bus Signals ....................3-3 System Bus Signals ....................3-3 MOTOROLA Contents...
Page 6 PowerPC RegistersÑSupervisor Registers............5-4 5.1.2.1 DAR, DSISR, and BAR Operation ..............5-5 5.1.2.2 Unsupported Registers .................5-6 5.1.2.3 PowerPC Supervisor-Level Register Bit Assignments ........5-6 5.1.2.3.1 Machine State Register (MSR) ..............5-6 5.1.2.3.2 Processor Version Register ..............5-8 5.1.3 MPC860-Specific SPRs..................5-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 7 Integer Load and Store String Instructions ..........6-14 6.2.4.3 Branch and Flow Control Instructions ............6-15 6.2.4.3.1 Branch Instruction Address Calculation ..........6-15 6.2.4.3.2 Branch Instructions ................6-16 6.2.4.3.3 Condition Register Logical Instructions ..........6-16 6.2.4.4 Trap Instructions ..................6-17 6.2.4.5 Processor Control Instructions ..............6-17 MOTOROLA Contents...
Page 8 Implementation-Specific Exceptions..............7-12 7.1.3.1 Software Emulation Exception (0x01000) ..........7-12 7.1.3.2 Instruction TLB Miss Exception (0x01100) ..........7-12 7.1.3.3 Data TLB Miss Exception (0x01200) ............7-13 7.1.3.4 Instruction TLB Error Exception (0x01300)..........7-13 7.1.3.5 Data TLB Error Exception (0x014000)............7-14 viii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 9 Data Cache Block Flush (dcbf)..............8-20 8.4.6 Data Cache Block Invalidate (dcbi)...............8-20 Instruction Cache Operations ................8-20 8.5.1 Instruction Cache Hit ..................8-22 8.5.2 Instruction Cache Miss...................8-22 8.5.3 Instruction Fetching on a Predicted Path ............8-23 8.5.4 Fetching Instructions from Caching-Inhibited Regions.........8-23 MOTOROLA Contents...
Page 10 DMMU Tablewalk Control Register (MD_TWC).........9-19 9.8.6 IMMU Real Page Number Register (MI_RPN)..........9-20 9.8.7 DMMU Real Page Number Register (MD_RPN)..........9-22 9.8.8 MMU Tablewalk Base Register (M_TWB) ...........9-23 9.8.9 MMU Current Address Space ID Register (M_CASID) .......9-23 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 11 Accessing Off-Core SPRs ................10-8 Chapter 11 System Interface Unit 11.1 Features ......................11-1 11.2 System Configuration and Protection ..............11-2 11.3 Multiplexing SIU Pins..................11-3 11.4 Programming the SIU..................11-4 11.4.1 Internal Memory Map Register (IMMR) ............11-4 11.4.2 SIU Module Configuration Register (SIUMCR) ...........11-5 MOTOROLA Contents...
Page 12 PIT Register (PITR) ..................11-33 11.12 General SIU Timers Operation.................11-33 11.12.1 Freeze Operation ..................11-33 11.12.2 Low-Power Stop Operation................11-34 Chapter 12 Reset 12.1 Types of Reset ....................12-1 12.1.1 Power-On Reset....................12-2 12.1.2 External Hard Reset..................12-2 12.1.3 Internal Hard Reset..................12-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 13 Bus Transfer Overview ..................14-1 14.3 Bus Interface Signal Descriptions ..............14-2 14.4 Bus Operations ....................14-6 14.4.1 Basic Transfer Protocol..................14-6 14.4.2 Single-Beat Transfer ..................14-7 14.4.2.1 Single-Beat Read Flow ................14-7 14.4.2.2 Single-Beat Write Flow ................14-9 14.4.3 Burst Transfers .....................14-13 14.4.4 Burst Operations...................14-14 MOTOROLA Contents xiii...
Page 14 SPLL Reset Configuration .................15-6 15.2.2.2 SPLL Output Characteristics and Stability ..........15-7 15.2.2.3 The System Phase-Locked Loop Pins (VDDSYN, VSSSYN, VSSSYN1, XFC) ...................15-8 15.2.2.4 Disabling the SPLL ..................15-9 15.3 Clock Signals......................15-9 15.3.1 Clocks Derived from the SPLL Output ............15-9 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 15 16.1 Features ......................16-1 16.2 Basic Architecture ....................16-4 16.3 Chip-Select Programming Common to the GPCM and UPM ......16-6 16.3.1 Address Space Programming .................16-7 16.3.2 Register Programming Order .................16-7 16.3.3 Memory Bank Write Protection ..............16-7 16.3.4 Address Type Protection ................16-7 MOTOROLA Contents...
Page 16 General-Purpose Signals (GxTx, GOx)............16-40 16.6.4.5 Loop Control (LOOP) ................16-42 16.6.4.6 Exception Pattern Entry (EXEN) .............16-43 16.6.4.7 Address Multiplexing (AMX) ..............16-43 16.6.4.8 Transfer Acknowledge and Data Sample Control (UTA, DLT3) ....16-47 16.6.4.9 Disable Timer Mechanism (TODT) ............16-48 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 17 Power Control ....................17-7 17.3.5 Reset and Three-State Control ...............17-7 17.3.6 DMA ......................17-7 17.4 Programming Model ..................17-8 17.4.1 PCMCIA Interface Input Pins Register (PIPR) ..........17-8 17.4.2 PCMCIA Interface Status Changed Register (PSCR) ........17-9 17.4.3 PCMCIA Interface Enable Register (PER)..........17-10 MOTOROLA Contents xvii...
Page 18 CP Command Register (CPCR) ..............19-6 19.5.3 CP Commands ....................19-7 19.5.3.1 CP Command Examples................19-8 19.5.3.2 CP Command Execution Latency ..............19-9 19.6 Dual-Port RAM ....................19-9 19.6.1 System RAM and Microcode Packages ............19-10 19.6.2 The Buffer Descriptor (BD) .................19-11 xviii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 19 IDMA Channel Operation................20-12 20.3.6.1 Activating an IDMA Channel ..............20-13 20.3.6.2 Suspending an IDMA Channel ..............20-13 20.3.7 IDMA Interface SignalsÑDREQ and SDACK...........20-13 20.3.7.1 IDMA Requests for Memory/Memory Transfers ........20-13 20.3.7.2 IDMA Requests for Peripheral/Memory Transfers .........20-14 20.3.7.2.1 Level-Sensitive Requests ..............20-14 MOTOROLA Contents...
Page 20 SI RAM Pointer Register (SIRP) .............21-26 21.2.5 IDL Bus Implementation................21-28 21.2.5.1 ISDN Terminal Adaptor Application ............21-28 21.2.5.2 Programming the IDL Interface ...............21-31 21.2.6 GCI Bus Implementation................21-32 21.2.6.1 GCI Activation/Deactivation..............21-34 21.2.6.2 Programming the GCI Interface ...............21-34 21.2.6.2.1 Normal Mode ..................21-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 21 22.3.7.4 Reset Sequence for an SCC Receiver ............22-27 22.3.7.5 Switching Protocols .................22-27 22.3.8 Saving Power ....................22-27 Chapter 23 SCC UART Mode 23.1 Features ......................23-2 23.2 Normal Asynchronous Mode ................23-3 23.3 Synchronous Mode.....................23-3 23.4 SCC UART Parameter RAM ................23-4 MOTOROLA Contents...
Page 22 24.13.2 SCC HDLC Programming Example #2 ............24-16 24.14 HDLC Bus Mode with Collision Detection .............24-16 24.14.1 HDLC Bus Features ..................24-19 24.14.2 Accessing the HDLC Bus................24-19 24.14.3 Increasing Performance ................24-20 24.14.4 Delayed RTS Mode ..................24-21 xxii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 23 Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC Mask Register (SCCM)................26-9 26.13.2 SCC Asynchronous HDLC Status Register (SCCS)........26-10 26.13.3 Asynchronous HDLC Mode Register (PSMR)..........26-11 26.14 SCC Asynchronous HDLC RxBDs..............26-11 26.15 SCC Asynchronous HDLC TxBDs..............26-13 26.16 Differences between HDLC and Asynchronous HDLC ........26-14 MOTOROLA Contents xxiii...
Page 24 Parallel CAM Interface.................28-10 28.8 SCC Ethernet Parameter RAM.................28-12 28.9 Programming the Ethernet Controller ..............28-14 28.10 SCC Ethernet Commands.................28-14 28.11 SCC Ethernet Address Recognition ..............28-16 28.12 Hash Table Algorithm ..................28-17 28.13 Interpacket Gap Time ..................28-18 xxiv MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 25 29.10 SCC Transparent Receive Buffer Descriptor (RxBD) ........29-9 29.11 SCC Transparent Transmit Buffer Descriptor (TxBD)........29-10 29.12 SCC Transparent Event Register (SCCE)/Mask Register (SCCM)....29-12 29.13 SCC Status Register in Transparent Mode (SCCS) .........29-13 29.14 SCC2 Transparent Programming Example ............29-13 MOTOROLA Contents...
Page 26 SMC Transparent Commands ..............30-25 30.4.8 Handling Errors in the SMC Transparent Controller ........30-26 30.4.9 SMC Transparent Receive BD (RxBD) ............30-26 30.4.10 SMC Transparent Transmit BD (TxBD)............30-27 30.4.11 SMC Transparent Event Register (SMCE)/Mask Register (SMCM) ..30-29 xxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 27 The SPI Buffer Descriptor (BD) Table ............31-13 31.7.1 SPI Buffer Descriptors (BDs) ..............31-14 31.7.1.1 SPI Receive BD (RxBD)................31-14 31.7.1.2 SPI Transmit BD (TxBD) ................31-15 31.8 SPI Master Programming Example..............31-17 31.9 SPI Slave Programming Example ..............31-18 31.10 Handling Interrupts in the SPI................31-19 MOTOROLA Contents xxvii...
Page 28 Control Character Table, RCCM, and RCCR ..........33-6 33.4 The PIP Registers ....................33-7 33.4.1 PIP Configuration Register (PIPC) ..............33-7 33.4.2 PIP Event Register (PIPE)................33-9 33.4.3 PIP Mask Register ..................33-10 33.4.4 PIP Timing Parameters Register (PTPR) .............33-10 33.4.5 The Port B Registers..................33-10 xxviii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 29 34.4.1.1 Port C Data Register (PCDAT)..............34-15 34.4.1.2 Port C Data Direction Register (PCDIR) ..........34-15 34.4.1.3 Port C Pin Assignment Register (PCPAR) ..........34-15 34.4.1.4 Port C Special Options Register (PCSO) ..........34-16 34.4.1.5 Port C Interrupt Control Register (PCINT)..........34-17 MOTOROLA Contents xxix...
Page 30 DSP Function Priority within the CPM..............36-6 36.10 DSP Event/Mask Registers (SDSR/SDMR)............36-7 36.11 FIR Library Functions ..................36-7 36.11.1 FIR1ÐReal C, Real X, and Real Y..............36-8 36.11.1.1 FIR1 Coefficient, Input, and Output Buffers ..........36-8 36.11.1.2 FIR1 Function Descriptor................36-9 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 31 LMS2 Applications ..................36-28 36.17 Weighted Vector Addition (WADD)ÐReal X and Real Y.......36-28 36.17.1 WADD Coefficients and Input Buffers............36-28 36.17.2 WADD Function Descriptor ................36-29 36.17.3 WADD Applications..................36-30 36.18 DSP Performance Using the Core Alone Versus Using the CPM ....36-30 MOTOROLA Contents xxxi...
Page 32 37.2.4.4 Ignore First Match ..................37-17 37.2.4.5 Generating Six Compare Types ...............37-18 37.2.5 Load/Store Breakpoint Example ..............37-18 37.3 Development System Interface.................37-19 37.3.1 Debug Mode Operation ................37-21 37.3.1.1 Debug Mode Enable vs. Debug Mode Disable ........37-22 xxxii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 33 Load/Store Support AND-OR Control Register (LCTRL2)....37-41 37.5.1.6 Breakpoint Counter Value and Control Registers (COUNTA/COUNTB).................37-43 37.5.2 Debug Mode Registers.................37-44 37.5.2.1 Interrupt Cause Register (ICR) ..............37-44 37.5.2.2 Debug Enable Register (DER) ..............37-46 37.5.2.3 Development Port Data Register (DPDR) ..........37-47 MOTOROLA Contents xxxiii...
Page 34 CLAMP ......................38-7 38.4.5 HIÐZ .......................38-7 38.5 TAP Usage Considerations.................38-7 38.6 Recommended TAP Configuration ..............38-8 38.7 Motorola MPC860 BSDL Description ...............38-8 Appendix A Byte Ordering Byte Ordering Overview ..................A-1 MPC860 Byte-Ordering Mechanisms ..............A-1 BE Mode......................A-2 TLE Mode......................A-2 A.4.1 TLE Mode System Examples................A-4 PPC-LE Mode......................A-6...
Page 35 MPC860-Specific SPRs ..................C-2 Appendix D MPC860 Instruction Set Listings Instructions Sorted by Mnemonic ............... D-1 Instructions Sorted by Opcode ................D-9 Instructions Grouped by Functional Categories..........D-17 Instructions Sorted by Form................D-27 Instruction Set Legend ..................D-38 MOTOROLA Contents xxxv...
Page 36 CONTENTS Paragraph Page Title Number Number xxxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 37 IMMU Real Page Number Register (MI_RPN) ..........9-21 9-12 DMMU Real Page Number Register (MD_RPN) ..........9-22 9-13 MMU Tablewalk Base Register (M_TWB) ............9-23 9-14 MMU Current Address Space ID Register (M_CASID)........9-23 9-15 MMU Access Protection Registers (MI_AP/MD_AP)........9-24 MOTOROLA Illustrations xxxvii...
Page 38 11-21 Timebase Reference Registers (TBREFA and TBREFB) ....... 11-25 11-22 Timebase Status and Control Register (TBSCR)..........11-26 11-23 Real-Time Clock Block Diagram ..............11-27 11-24 Real-Time Clock Status and Control Register (RTCSC) ........ 11-27 xxxviii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 39 Internal Operand Representation ..............14-24 14-20 Interface to Different Port Size Devices ............14-24 14-21 Bus Arbitration Flowchart ................14-26 14-22 Masters Signals Basic Connection..............14-27 14-23 Bus Arbitration Timing Diagram..............14-28 14-24 Internal Bus Arbitration State Machine ............14-29 MOTOROLA Illustrations xxxix...
Page 40 Memory Periodic Timer Prescaler Register (MPTPR)........16-17 16-15 GPCM-to-SRAM Configuration..............16-18 16-16 GPCM Peripheral Device Interface ..............16-20 16-17 GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0)....16-20 16-18 GPCM Memory Device Interface..............16-21 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 41 Synchronous External Master Interconnect Example........16-55 16-50 Synchronous External Master: Burst Read Access to Page Mode DRAM ..16-56 16-51 Asynchronous External Master Interconnect Example........16-57 16-52 Asynchronous External Master Timing Example..........16-58 16-53 Page-Mode DRAM Interface Connection ............16-59 MOTOROLA Illustrations...
Page 42 CPM Block Diagram..................18-2 18-2 MPC860 Application Design Example.............. 18-4 18-3 CPM Timer Block Diagram................18-5 18-4 Timer Cascaded Mode Block Diagram.............. 18-7 18-5 Timer Global Configuration Register (TGCR)..........18-8 18-6 Timer Mode Registers (TMR1ÐTMR4)............. 18-9 xlii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 43 SI RAM Partitioning Using Two TDMs with Dynamic Frames ..... 21-13 21-10 SIRAM Entry ....................21-14 21-11 Example Using SI RAMn[SWTR] ..............21-15 21-12 SI Global Mode Register (SIGMR) ..............21-17 21-13 SI Mode Register (SIMODE) ................21-18 MOTOROLA Illustrations xliii...
Page 44 SCC UART Receiving using RxBDs .............. 23-16 23-8 SCC UART RxBD................... 23-17 23-9 SCC UART Transmit Buffer Descriptor (TxBD)..........23-18 23-10 SCC UART Interrupt Event Example.............. 23-20 23-11 SCC UART Event Register (SCCE) and Mask Register (SCCM) ....23-20 xliv MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 45 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)....27-15 27-9 SCC Status Registers (SCCS)................27-16 28-1 Ethernet Frame Structure ................... 28-1 28-2 Ethernet Block Diagram ..................28-2 28-3 Connecting the MPC860 to Ethernet ..............28-6 28-4 MPC860 Ethernet Serial CAM Interface............28-10 MOTOROLA Illustrations...
Page 46 SPI Transfer Format with SPMODE[CP] = 1 ........... 31-8 31-7 SPI Event/Mask Registers (SPIE/SPIM) ............31-10 31-8 SPI Command Register (SPCOM)..............31-10 31-9 Receive/Transmit Function Code Registers (RFCR/TFCR)......31-12 31-10 SPI Memory Structure ..................31-13 xlvi MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 47 34-2 Port A Data Register (PADAT) ................. 34-4 34-3 Port A Data Direction Register (PADIR) ............34-5 34-4 Port A Pin Assignment Register (PAPAR)............34-5 34-5 Block Diagram for PA15 (True for all Non-Open-Drain Port Signals)..... 34-7 MOTOROLA Illustrations xlvii...
Page 48 FIR5 Fractionally Spaced Equalizer Example..........36-17 36-21 FIR6 Function Descriptor ................36-18 36-22 IIR Function ..................... 36-19 36-23 IIR Function Descriptor ................... 36-20 36-24 MOD Function ....................36-21 36-25 MOD Function Descriptor ................36-22 xlviii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 49 Observe-Only Input Signal Boundary Scan Cell (Input Cell) ......38-4 38-5 Input/Output Control Boundary Scan Cell (I/O Control Cell)......38-5 38-6 Bidirectional (I/O) Signal Boundary Scan Cell ..........38-5 38-7 Bypass Register....................38-7 TLE Mode Mechanisms..................A-3 MOTOROLA Illustrations xlix...
Page 50 ILLUSTRATIONS Figure Page Title Number Number Byte Swapping ....................A-4 PPC-LE Mode Mechanisms................A-7 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 51 Integer Load and Store with Byte-Reverse Instructions........6-14 6-10 Integer Load and Store Multiple Instructions............6-14 6-11 Integer Load and Store String Instructions............6-14 6-12 Branch Instructions....................6-16 6-13 Condition Register Logical Instructions..............6-16 6-14 Trap Instructions....................6-17 6-15 Move to/from Condition Register Instructions............6-17 MOTOROLA Contents...
Page 52 DC_DAT Format when Reading a Tag..............8-15 8-11 Copyback Buffer Select Field (DC_CST[21Ð27]) Encoding ........ 8-15 Identical Entries Required in Level-One/Level-Two Tables ........ 9-11 Number of Replaced EA Bits per Page Size ............9-13 Level-One Segment Descriptor Format..............9-13 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 53 TBU Field Descriptions..................11-25 11-17 TBL Field Descriptions ..................11-25 11-18 TBREFA/TBREFB Field Descriptions ............... 11-26 11-19 TBSCR Field Descriptions .................. 11-26 11-20 RTCSC Field Descriptions .................. 11-28 11-21 RTC Field Description ..................11-28 11-22 RTCAL Field Descriptions.................. 11-29 MOTOROLA Contents liii...
Page 54 Boot Bank Field Values after Reset ..............16-28 16-13 RAM Word Bit Settings ..................16-36 16-14 Enabling Byte-Selects ..................16-40 16-15 GPL_X5 Signal Behavior..................16-41 16-16 MxMR Loop Field Usage..................16-43 16-17 Address Multiplexing ..................16-44 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 55 20-9 Single-Buffer Mode IDMA1 Parameter RAM Map ........... 20-18 20-10 DCMR Field Descriptions (Single-Buffer Mode)..........20-19 21-1 TSA Signals......................21-7 21-2 SIRAM Field Descriptions .................. 21-14 21-3 Example SI RAM Entry Settings for an IDL Bus ..........21-16 MOTOROLA Contents...
Page 56 24-7 SCC HDLC RxBD Status and Control Field Descriptions ........24-9 24-8 SCC HDLC TxBD Status and Control Field Descriptions ......... 24-11 24-9 SCCE/SCCM Field Descriptions ................ 24-12 24-10 HDLC SCCS Field Descriptions ................. 24-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 57 29-4 Receive Commands ....................29-8 29-5 Transmit Errors...................... 29-8 29-6 Receive Errors ....................... 29-8 29-7 SCC Transparent RxBD Status and Control Field Descriptions ......29-9 29-8 SCC Transparent Tx BD Status and Control Field Descriptions ......29-11 MOTOROLA Contents lvii...
Page 58 I2BRG Field Descriptions ..................32-8 32-4 I2CER/I2CMR Field Descriptions ................ 32-8 32-5 I2COM Field Descriptions ..................32-9 32-6 C Parameter RAM Memory Map ............... 32-9 32-7 RFCR/TFCR Field Descriptions ................. 32-11 32-8 C Transmit/Receive Commands............... 32-11 lviii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 59 Interrupt Vector Encodings ................... 35-6 35-3 CICR Field Descriptions ..................35-7 35-4 CIVR Field Descriptions ..................35-10 36-1 DSP Library Functions ..................36-2 36-2 FD Status and Control Bits..................36-4 36-3 DSPx Parameter RAM Memory Map ..............36-6 MOTOROLA Contents...
Page 60 Status/Data Shifted Out of Development Port Shift Register ......37-32 37-13 Debug Instructions/Data Shifted Into Development Port Shift Register..... 37-33 37-14 MPC860-Specific Development Support and Debug SPRs........ 37-36 37-15 Development Support/Debug Registers Protection..........37-37 37-16 CMPAÐCMPD Field Descriptions ..............37-37 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 61 Integer Store Instructions ..................D-22 D-15 Integer Load and Store with Byte-Reverse Instructions........D-22 D-16 Integer Load and Store Multiple Instructions............D-22 D-17 Integer Load and Store String Instructions............D-23 D-18 Memory Synchronization Instructions ..............D-23 D-19 Floating-Point Load Instructions6................ D-23 MOTOROLA Contents...
Page 62 D-38 XFX-Form ......................D-34 D-39 XFL-Form......................D-34 D-40 XS-Form ....................... D-34 D-41 XO-Form ......................D-34 D-42 A-Form ......................... D-35 D-43 M-Form......................... D-36 D-44 MD-Form......................D-36 D-45 MDS-Form ......................D-37 D-46 Instruction Set Legend..................D-38 lxii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 63: About This Book
About This Book The primary objective of this manual is to help communications system designers build systems using the Motorola MPC860 and to help software designers provide operating systems and user-level applications to take fullest advantage of the MPC860. Although this book describes aspects regarding the PowerPCª architecture that are critical for understanding the MPC860 core, it does not contain a complete description of the architecture.
Page 64: Organization
Ñ Chapter 10, ÒInstruction Execution Timing,Ó describes the MPC860 instruction unit, and provides ways to make greatest advantage of its RISC architecture characteristics, such as pipelining and parallel execution. It includes a table of instruction latencies and lists dependencies and potential bottlenecks. lxiv MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 65 DMA (SDMA) channels on the MPC860 with which the CP implements sixteen virtual SDMA channels. Ñ Chapter 21, ÒSerial Interface,Ó describes the serial interface (SI) in which the physical interface to all SCCs and SMCs is implemented. MOTOROLA About This Book...
Page 66 I/O and allows data to be sent to and from the MPC860 over 8 or 16 parallel data lines with two handshake control signals. Ñ Chapter 34, ÒParallel I/O Ports,Ó describes the four general-purpose I/O lxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 67 ¥ Appendix C, ÒRegister Quick Reference Guide,Ó contains a quick reference guide to the MPC860 registers. ¥ Appendix D, ÒMPC860 Instruction Set Listings,Ó contains tables of the PowerPC instructions supported by the MPC860. ¥ This manual also includes a glossary and an index. MOTOROLA About This Book lxvii...
Page 68: Suggested Reading
60x family of PowerPC microprocessors. ¥ PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide (Motorola order #: MPCPRG/D) is a concise reference that includes the register summary, memory control model, exception vectors, and the PowerPC instruction set.
Page 69: Conventions
In certain contexts, such as in a signal encoding or a bit Þeld, indicates a donÕt care. Used to express an undeÞned numerical value Â NOT logical operator & AND logical operator OR logical operator MOTOROLA About This Book lxix...
Page 70: Acronyms And Abbreviations
Register used for determining the source of a DSI exception Digital signal processing DTLB Data translation lookaside buffer Effective address EEST Enhanced Ethernet serial transceiver EPROM Erasable programmable read-only memory Floating-point register FPSCR Floating-point status and control register MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 71 Multiply accumulate MESI ModiÞed/exclusive/shared/invalidÑcache coherency protocol Memory management unit Most-signiÞcant byte Most-signiÞcant bit Machine state register Not a number Next instruction address NMSI Nonmultiplexed serial interface No-op No operation Operating environment architecture Open systems interconnection MOTOROLA About This Book lxxi...
Page 72 SRR0 Machine status save/restore register 0 SRR1 Machine status save/restore register 1 Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UIMM Unsigned immediate value lxxii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 73: Powerpc Architecture Terminology Conventions
Instruction storage interrupt (ISI) ISI exception Interrupt Exception Privileged mode (or privileged state) Supervisor-level privilege Problem mode (or problem state) User-level privilege Real address Physical address Relocation Translation Storage (locations) Memory Storage (the act of) Access MOTOROLA About This Book lxxiii...
Page 74 Table iii. Instruction Field Conventions The Architecture SpeciÞcation Equivalent to: BA, BB, BT crbA, crbB, crbD (respectively) BF, BFA crfD, crfS (respectively) RA, RB, RT, RS rA, rB, rD, rS (respectively) SIMM UIMM /, //, /// 0...0 (shaded) lxxiv MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 75: Intended Audience
Book titles in text are set in italics. PreÞx to denote hexadecimal number PreÞx to denote binary number rA, rB Instruction syntax used to identify a source GPR Instruction syntax used to identify a destination GPR MOTOROLA Part I. Overview...
Page 76: Acronyms And Abbreviations
Infrared Data Association ISDN Integrated services digital network ITLB Instruction translation lookaside buffer Integer unit JTAG Joint Test Action Group Least recently used (cache replacement algorithm) Load/store unit Memory management unit Machine state register I-ii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 77 Serial peripheral interface Special-purpose register SRAM Static random access memory Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UISA User instruction set architecture User-programmable machine Virtual environment architecture MOTOROLA Part I. Overview I-iii...
Page 78 Part I. Overview I-iv MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 79: Mpc860 Overview
Unless otherwise speciÞed, the PowerQUICC unit is referred to as the MPC860 in this manual. The MPC860 is a PowerPC architecture-based derivative of MotorolaÕs MC68360 Quad Integrated Communications Controller (QUICCª). The CPU on the MPC860 is a 32-bit PowerPC implementation that incorporates memory management units (MMUs) and instruction and data caches.
Page 80 Ñ Software watchdog Ñ Periodic interrupt timer (PIT) Ñ Low-power stop mode Ñ Clock synthesizer Ñ PowerPC decrementer and time base Ñ Real-time clock (RTC) Ñ Reset controller Ñ IEEE 1149.1 test access port (JTAG) MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 81 Ñ AppleTalk Ñ Universal asynchronous receiver transmitter (UART) Ñ Synchronous UART Ñ Serial infrared (IrDA) Ñ Binary synchronous communication (BISYNC) Ñ Totally transparent (bit streams) Ñ Totally transparent (frame based with optional cyclic redundancy check (CRC)) MOTOROLA Chapter 1. MPC860 Overview...
Page 82 PLL active for fast wake up Ñ Deep sleepÑAll units disabled including PLL except RTC, PIT, time base, and decrementer. Ñ Power down modeÑ All units powered down except PLL, RTC, PIT, time base and decrementer MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 83: Architecture Overview
1.2 Architecture Overview The MPC860 integrates an embedded PowerPC core with high-performance, low-power peripherals to extend the Motorola Data Communications family of embedded processors even farther into high-end communications and networking products. The MPC860 is comprised of three modules that each use the 32-bit internal bus: the PowerPC core, the system integration unit (SIU), and the communication processor module (CPM).
Page 84: Embedded Powerpc Core
The core can compare using =, ¹, <, > conditions to generate watchpoints. Each watchpoint can then generate a break point that can be programmed to trigger in a programmable number of events. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 85: System Interface Unit (Siu)
A gear mode is provided which is determined by a clock divider, allowing the operating system to reduce the operational frequency of the processor. Doze mode disables core functional units other MOTOROLA Chapter 1. MPC860 Overview...
Page 86: Communications Processor Module (Cpm)
(MAC) function on the CPM further enhances the MPC860, enabling various modem and DSP applications. Because the CPM architectural approach remains intact between the MPC860 and the MC68360 QUICC, a user of the MC68360 QUICC can easily become familiar with the MPC860. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 87: Software Compatibility Issues
CPU commands, address, and serial request which are useful for software debugging. Support for single-step operation with all CPM registers visible further simpliÞes software development for the CPM. MOTOROLA Chapter 1. MPC860 Overview...
Page 88 Part I. Overview 1-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 89: Memory Map
32 bits 17.4.5/17-12 POR2ÑPCMCIA interface option register 2 32 bits 17.4.6/17-13 PBR3ÑPCMCIA interface base register 3 32 bits 17.4.5/17-12 POR3ÑPCMCIA interface option register 3 32 bits 17.4.6/17-13 PBR4ÑPCMCIA interface base register 4 32 bits 17.4.5/17-12 MOTOROLA Chapter 2. Memory Map...
Page 90 OR6ÑOption register bank 6 32 bits 16.4.2/16-10 BR7ÑBase register bank 7 32 bits 16.4.1/16-8 OR7ÑOption register bank 7 32 bits 16.4.2/16-10 140Ð163 Reserved 36 bytes Ñ MARÑMemory address register 32 bits 16.4.7/16-17 MCRÑMemory command register 32 bits 16.4.5/16-15 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 91 System Integration Timers Keys TBSCRKÑTimebase status and control register 32 bits 11.4.5/11-11 TBREFAKÑTimebase reference register A key 32 bits 11.4.5/11-11 TBREFBKÑTimebase reference register B key 32 bits 11.4.5/11-11 TBKÑTimebase/decrementer register key 32 bits 11.4.5/11-11 MOTOROLA Chapter 2. Memory Map...
Page 92 32 bits 20.2.4/20-5 SDSRÑSDMA status register 8 bits 20.2.2/20-4 909Ð90B Reserved 3 bytes Ñ SDMRÑSDMA mask register 8 bits 20.2.3/20-5 90DÐ90F Reserved 3 bytes Ñ IDSR1ÑIDMA1 status register 8 bits 20.3.9.2/20-19 911Ð913 Reserved 3 bytes Ñ MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 93 TMR1ÑTimer 1 mode register 16 bits 18.2.3.2/18-9 TMR2ÑTimer 2 mode register 16 bits 18.2.3.2/18-9 TRR1ÑTimer 1 reference register 16 bits 18.2.3.3/18-10 TRR2ÑTimer 2 reference register 16 bits 18.2.3.3/18-10 TCR1ÑTimer 1 capture register 16 bits 18.2.3.4/18-10 MOTOROLA Chapter 2. Memory Map...
Page 94 Baud Rate Generators BRGC1ÑBRG1 conÞguration register 32 bits 21.4.1/21-40 BRGC2ÑBRG2 conÞguration register 32 bits 21.4.1/21-40 9F8Ð9FF Reserved 8 bytes Ñ SCC1 GSMR_L1ÑSCC1 general mode register 32 bits 22.1.1/22-3 GSMR_H1ÑSCC1 general mode register 32 bits 22.1.1/22-3 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 95 23.20/23-21 (UART) 24.11/24-12 (HDLC) 26.13.1/26-9 (Asynchronous HDLC) 27.15/27-16 (BISYNC) 29.13/29-13 (Transparent) Reserved 16 bits Ñ SCCM2ÑSCC2 mask register 16 bits 23.20/23-21 (UART) 24.12/24-14 (HDLC) 26.13.3/26-11 (Asynchronous HDLC) 27.15/27-16 (BISYNC) 29.13/29-13 (Transparent) Reserved 8 bits Ñ MOTOROLA Chapter 2. Memory Map...
Page 96 DSR4ÑSCC4 data synchronization register 16 bits 22.1.3/22-10 SCCE4ÑSCC4 event register 16 bits 23.20/23-21 (UART) 24.12/24-14 (HDLC) A72ÐA73 Reserved 2 bytes 26.13.3/26-11 (Asynchronous HDLC) SCCM4ÑSCC4 mask register 16 bits 27.15/27-16 (BiSYNC) 29.13/29-13 (Transparent) Reserved 1 byte Ñ MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 97 31.4.3/31-10 AAEÐAB1 Reserved 4 bytes Ñ Parallel Interface Port(PIP) PIPCÑPIP conÞguration register 16 bits 33.4.1/33-7 AB4ÐAB5 Reserved 2 bytes Ñ PTPRÑPIP timing parameters register 16 bits 33.4.4/33-10 PBDIRÑPort B data direction register 32 bits 34.3.1.3/34-10 MOTOROLA Chapter 2. Memory Map...
Page 98 Specialized RAM C00ÐDFF SIRAMÑSI routing RAM 21.2.3.7/21-14 bytes E00Ð1FFF Reserved 4,608 Ñ bytes Dual-Ported RAM 2000Ð2FFF DPRAMÑDual-ported RAM 4,096 19.6/19-9 bytes 3000Ð3BFF DPRAMÑDual-ported RAM expansion (reserved) 3,072 Ñ bytes 3C00Ð3FFF PRAMÑParameter RAM 1,024 19.6.3/19-11 bytes 2-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 99: Hardware Interface Overview
¥ Easy to interface to slave devices ¥ Bus is synchronous (all signals are referenced to rising edge of bus clock) ¥ Contains supports for data parity The MPC860 bus interface signals are shown in Figure 3-1. MOTOROLA Chapter 3. Hardware Interface Overview...
Page 100 TxD3/PD10 ALE_B/DSCK/AT1 RxD4/PD9 WAIT_B TxD4/PD8 IP_B[0Ð1]/WP[0Ð1]/VFLS[0Ð1] RTS3/PD7 IP_B2/IOIS16_B /AT2 RTS4/PD6 IP_B3/WP2/VF2 REJECT2 /PD5 IP_B4/LWP0/VF0 REJECT3 /PD4 IP_B5/LWP1/VF1 REJECT4 /PD3 IP_B6/DSDI/AT0 IP_B7/PTR/VAT3 DSDI/TDI OP[0Ð1] DSCK/TCK OP2/MODCK1/STS TRST OP3/MODCK2/DSDO DSDO/TDO BADDR30/REG BADDR[28Ð29] Figure 3-1. MPC860 External Signals MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 101: System Bus Signals
Burst TransactionÑThis signal is driven by the bus master to indicate that the current Three-state initiated transfer is a burst. The MPC860 drives this signal when it is bus master. This signal is input when an external master initiates a transaction on the bus. MOTOROLA Chapter 3. Hardware Interface Overview...
Page 102 Interrupt Request 2ÑOne of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 103 Parity generation and checking is not supported for external masters. Interrupt Request 5ÑOne of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. MOTOROLA Chapter 3. Hardware Interface Overview...
Page 104 BR7 and OR7 in the memory controller. Card Enable 2 Slot BÑThis output enables odd byte transfers when accesses to the PCMCIA Slot B are handled under the control of the PCMCIA interface. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 105 UPMA when an external transfer to a slave is controlled by UPMA. General-Purpose Line 1 on UPMBÑThis output reßects the value speciÞed in the UPMB when an external transfer to a slave is controlled by UPMB. MOTOROLA Chapter 3. Hardware Interface Overview...
Page 106 PCMCIA Slot A are handled under the control of the PCMCIA interface. CE2_A Output Card Enable 2 Slot AÑThis output enables odd byte transfers when accesses to PCMCIA Slot A are handled under the control of the PCMCIA interface. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 107 ßow executed by the core. Visible Instruction Queue Flushes StatusÑThe MPC860 outputs VF0 with VF1/VF2 when instruction ßow tracking is required. VFn reports the number of instructions ßushed from the instruction queue in the core. MOTOROLA Chapter 3. Hardware Interface Overview...
Page 108 PCMCIA interface, this signal duplicates the value of TSIZ0/REG. When an external master initiates an access, REG is output by the PCMCIA interface (if it must handle the transfer) to indicate the space in the PCMCIA card being accessed. 3-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 109 CLK3ÑOne of eight clock inputs that can be used to clock SCCs and SMCs. TIN2ÑTimer 2 external clock input. TIN2 L1TCLKA L1TCLKAÑTransmit clock for the serial interface TDM port A. BRGO2 BRGO2ÑOutput clock of BRG2. MOTOROLA Chapter 3. Hardware Interface Overview 3-11...
Page 110 C serial clock pin. Bidirectional; should be conÞgured as an open-drain BRGO2 Open-drain) output. BRGO2ÑBRG2 output clock. PB[25] Bidirectional General-Purpose I/O Port B Bit 25ÑBit 25 of the general-purpose I/O port B. SMTXD1 (Optional: SMTXD1ÑSMC1 transmit data output. Open-drain) 3-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 111 Bidirectional General-Purpose I/O Port C Bit 13ÑBit 13 of the general-purpose I/O port C. L1RQB L1RQBÑD-channel request signal for the serial interface TDM port B. L1ST3 L1ST3ÑOne of four output strobes that can be generated by the serial interface. MOTOROLA Chapter 3. Hardware Interface Overview 3-13...
Page 112 Bidirectional General-Purpose I/O Port D Bit 10ÑBit 10 of the general-purpose I/O port D. TXD3 TXD3ÑTransmit data for serial channel 3. PD[9] Bidirectional General-Purpose I/O Port D Bit 9ÑBit 9 of the general-purpose I/O port D. RXD4 RXD4ÑReceive data for serial channel 4. 3-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 113 VDDSYNÑPower supply of the PLL circuitry. KAPWRÑPower supply of the internal OSCM, RTC, PIT, DEC, and TB. VSSÑGround for circuits, except for the PLL circuitry. VSSSYN, VSSSYN1ÑGround for the PLL circuitry. NOTE: * See Figure 13-2. MOTOROLA Chapter 3. Hardware Interface Overview 3-15...
Page 114 Part I. Overview 3-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 115 ¥ Chapter 9, ÒMemory Management Unit (MMU)Ó describes how the PowerPC MMU model is implemented on the MPC860. Although the MPC860 MMU is based on the PowerPC MMU model, it differs greatly in many respects, which are described in this chapter. MOTOROLA Part II. PowerPC Microprocessor Module II-i...
Page 116 60x family of PowerPC microprocessors. ¥ PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide (Motorola order #: MPCPRG/D) is a concise reference that includes the register summary, memory control model, exception vectors, and the PowerPC instruction set.
Page 117 Part II. PowerPC Microprocessor Module For a current list of useful Motorola documentation, refer to the world-wide web at http:// www.motorola.com/SPS/RISC/netcomm and at http://www.mot.com/SPS/PowerPC/. Conventions This chapter uses the following notational conventions: Bold entries in Þgures and tables showing registers and parameter Bold RAM should be initialized by the user.
Page 118 Least recently used Least-signiÞcant byte Least-signiÞcant bit Load/store unit Memory management unit Most-signiÞcant byte Most-signiÞcant bit Machine state register Not a number No-op No operation Operating environment architecture Peripheral component interconnect Processor version register II-iv MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 119 Data storage interrupt (DSI) DSI exception Extended mnemonics SimpliÞed mnemonics Instruction storage interrupt (ISI) ISI exception Interrupt Exception Privileged mode (or privileged state) Supervisor-level privilege Problem mode (or problem state) User-level privilege Real address Physical address MOTOROLA Part II. PowerPC Microprocessor Module II-v...
Page 120 Table vii. Instruction Field Conventions The Architecture SpeciÞcation Equivalent to: BA, BB, BT crbA, crbB, crbD (respectively) BF, BFA crfD, crfS (respectively) RA, RB, RT, RS rA, rB, rD, rS (respectively) SIMM UIMM /, //, /// 0...0 (shaded) II-vi MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 121: The Powerpc Core
ÒMPC860 Instruction Set.Ó 4.1 PowerPC Architecture Overview The PowerPC architecture, developed jointly by Motorola, IBM, and Apple Computer, is based on the POWERª architecture implemented by RS/6000ª family of computers. The PowerPC architecture takes advantage of recent technological advances in such areas as...
Page 122 ¥ Support for 64-bit addressing. The architecture supports both 32-bit or 64-bit implementations. This document describes the 32-bit portion of the PowerPC architecture. For information about the 64-bit architecture, see PowerPC Microprocessor Family: The Programming Environments. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 123: Levels Of The Powerpc Architecture
UISA and the VEA levels. For a more detailed discussion of the characteristics of the PowerPC architecture, see the Programming Environments Manual. For details regarding the MPC860 as a PowerPC implementation, see Section 4.6, ÒThe MPC860 and the PowerPC Architecture.Ó MOTOROLA Chapter 4. The PowerPC Core...
Page 124: Features
¥ Power Dissipation Control ¥ Time Base Counter ¥ Decrementer ¥ JTAG 32-Bit ¥ BDM interface 4 Kbyte 4 Kbyte Tags Tags ¥ Clock Multiplier D-Cache I-Cache U-Bus Interface Figure 4-1. Block Diagram of the Core MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 125: Basic Structure Of The Core
Ñ Load/store unit (LSU)ÑImplements all load and store instructions except ßoating-point load/store instructions. Note that because the MPC860 does not implement ßoating-point load and store instructions, this document refers to integer load/store instructions simply as load/store instructions. MOTOROLA Chapter 4. The PowerPC Core...
Page 126: Instruction Flow
This information is used to enable out-of-order completion of instructions and ensure a precise exception model. An instruction can be retired after all instructions ahead of it have retired and it updates the architected destination registers without taking an exception. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 127: Basic Instruction Pipeline
To reduce the latency caused by misprediction, PowerPC branch instructions allow the programmer to indicate whether a branch is likely to be taken. This is called static branch prediction. MOTOROLA Chapter 4. The PowerPC Core...
Page 128 PowerPC UISA) determines which instruction stream is prefetched while the branch is being resolved. When the branch operand becomes available, it is forwarded to the BPU and the condition is evaluated. The static branch prediction mechanism is shown in Table 4-1. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 129: Dispatching Instructions
As shown in Figure 4-1, the MPC860 allows parallel execution of instructions using separate branch processing unit (BPU), load/store unit (LSU), and integer unit (IU). These execution units are described in the following sections. MOTOROLA Chapter 4. The PowerPC Core...
Page 130: Branch Processing Unit
The following lists the LSUÕs main features: ¥ All instructions implemented in hardware, including unaligned, string, and multiple accesses ¥ Two-entry load/store instruction address queue 4-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 131 Figure 4-5. LSU Functional Block Diagram To execute multiple/string instructions and unaligned accesses, the LSU increments the EA to access all necessary data. This allows the LSU to execute unaligned accesses without stalling the master instruction pipeline. MOTOROLA Chapter 4. The PowerPC Core 4-11...
Page 132: Executing Load/Store Instructions
4.5.3.4 Nonspeculative Load Instructions Load instructions targeted at nonspeculative memory are identiÞed as nonspeculative one clock cycle after the previous load/store bus cycle ends, only if all prior instructions have Þnished without an exception. 4-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 133: Unaligned Accesses
LSU. The external bus interface implements memory reservations as they relate to accesses made by external bus devices. Accesses made by other internal devices to internal memories implement memory reservations as they relate to special internal bus snoop logic. MOTOROLA Chapter 4. The PowerPC Core 4-13...
Page 134: The Mpc860 And The Powerpc Architecture
MPC860 (such as TLBs) and some of which are not, such as the eciwx and ecowx instructions. ¥ The PowerPC architecture deÞnes features, such as virtual memory and ßoating-point instructions, that are not implemented on the MPC860. 4-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 135 For load with update and store with update instructions where rA = 0, the EA is written into r0. For load/store with load with update instructions where rA = rD, rA is boundedly undeÞned. update instructions MOTOROLA Chapter 4. The PowerPC Core 4-15...
Page 136 See Section 4.5.3.5, ÒUnaligned Accesses for a description of integer unaligned instruction execution and timing and to Section 10.2.2, ÒString Instruction Latency,Ó for a description of string instruction timing. 4-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 137 This memory is part of the main memory as seen by the core but cannot be accessed by any external system device. MOTOROLA Chapter 4. The PowerPC Core 4-17...
Page 138 TLB error exception mechanism when writing to an unmodiÞed page. Memory Two protection modes are supported by the MPC860: protection ¥ Domain manager mode ¥ PowerPC mode See Chapter 9, ÒMemory Management Unit (MMU).Ó 4-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 139: Powerpc Core Register Set
These are described brießy in Section 5.1.3, ÒMPC860-SpeciÞc SPRs,Ó but are described thoroughly in later chapters. Table 5-9 and Table 2-1 provide cross references to the sections in this book where each register is described. MOTOROLA Chapter 5. PowerPC Core Register Set...
Page 140: Powerpc Registersñuser Registers
The condition register (CR) is a 32-bit register that reßects the result of certain operations and provides a mechanism for testing and branching. The bits in the CR are grouped into eight 4-bit Þelds, CR0ÐCR7, as shown in Figure 5-1. Figure 5-1. Condition Register (CR) MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 141: Condition Register Cr0 Field Definition
5.1.1.1.3 XER Figure 5-2 shows XER bit assignments. Settings are based on the Þnal result produced by executing an instruction. Field Ñ Reset 0000_0000_0000_0000 Field Ñ BCNT Reset 0000_0000_0000_0000 Figure 5-2. XER Register MOTOROLA Chapter 5. PowerPC Core Register Set...
Page 142: Time Base Registers
SPRs, except for the machine state register (MSR), described in Table 5-5 Table 5-5. Supervisor-Level PowerPC Registers Description Name Comments Serialize Access Machine state register See Section 5.1.2.3.1, ÒMachine State Register Write fetch sync (MSR).Ó MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 143: Dar, Dsisr, And Bar Operation
For a data MMU error, the data MMU loads the DSISR with error status. For alignment exceptions, the DSISR is loaded with the instruction information as deÞned by the PowerPC architecture. MOTOROLA Chapter 5. PowerPC Core Register Set...
Page 144: Unsupported Registers
The 32-bit machine state register (MSR) is used to conÞgure such parameters as the privilege level, whether translation is enabled, and the endian-mode. It can be read by the mfmsr instruction and modiÞed by the mtmsr, sc, and rÞ instructions. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 145 1 The processor can execute ßoating-point instructions. (This setting is invalid on the MPC860) Machine check enable 0 Machine check exceptions are disabled. 1 Machine check exceptions are enabled. Ñ Reserved MOTOROLA Chapter 5. PowerPC Core Register Set...
Page 146: Processor Version Register
5.1.3 MPC860-SpeciÞc SPRs Table 5-2 and Table 5-9 list SPRs speciÞc to the MPC860. Debug registers, which have additional protection, are described in Chapter 37, ÒSystem Development and Debugging.Ó MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 147 Read Register 0 (MI_RAM0)Ó 11001 10010 MI_RAM1 Section 9.8.13, ÒDMMU RAM Entry Write (as a store) Read Register 1 (MD_RAM1)Ó 11000 11000 MD_CTR Section 9.8.2, ÒDMMU Control Write (as a store) Register (MD_CTR).Ó MOTOROLA Chapter 5. PowerPC Core Register Set...
Page 148 Fetch sync on write 00100 10011 CMPD Fetch sync on write 00100 10100 Fetch sync on write 00100 10101 Fetch sync on write 00100 10110 COUNTA Fetch sync on write 00100 10111 COUNTB Fetch sync on write 5-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 149 A system reset interrupt occurs when a nonmaskable interrupt is generated either by the software watchdog timer or the assertion of IRQ0. The only registers affected by the system reset interrupt are MSR, SRR0, and SRR1; no other reset activity occurs. Section 7.1.2.1, MOTOROLA Chapter 5. PowerPC Core Register Set 5-11...
Page 150 ¥ LCTRL2ÑCleared. ¥ COUNTA[16Ð31]ÑCleared. ¥ COUNTB[16Ð31]ÑCleared. ¥ ICRÑCleared (no exception occurred). ¥ DER[2,14,28Ð31]ÑSet (all debug-speciÞc exceptions cause debug mode entry). Reset values for memory-mapped registers are provided with individual register descriptions throughout this manual. 5-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 151 Operands for single-register memory access instructions have the characteristics shown in Table 6-1. (Although not permitted as memory operands, quad words are shown because quad-word alignment is desirable for certain memory operands.) MOTOROLA Chapter 6. MPC860 Instruction Set...
Page 152 ¥ Trap instructionsÑThese instructions are used to test for a speciÞed set of conditions; see Section 6.2.4.4, ÒTrap Instructions,Ó for more information. ¥ Processor control instructionsÑThese instructions are used for synchronizing memory accesses and managing caches and TLBs. For more information, see Sections 6.2.4.5, 6.2.5.1, and 6.2.6.2. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 153 In future versions of the PowerPC architecture, instruction codings that are now illegal may become assigned to instructions in the architecture, or may be reserved by being assigned to processor-speciÞc instructions. MOTOROLA Chapter 6. MPC860 Instruction Set...
Page 154 Section A.2, ÒInstructions Sorted by Opcode,Ó in the Programming Environments Manual and Section 6.2.1.4, ÒReserved Instruction Class.Ó Notice that extended opcodes for instructions that are defined only for 64-bit implementations are illegal in 32-bit implementations, and vice versa. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 155 Manual. 6.2.2.1 Memory Addressing A program references memory using the effective (logical) address computed by the processor when it executes a memory access or branch instruction or when it fetches the next sequential instruction. MOTOROLA Chapter 6. MPC860 Instruction Set...
Page 156 ¥ Previous instructions complete execution in the context (privilege, protection, and address translation) under which they were issued. ¥ The instructions following the sc or rÞ instruction execute in the context established by these instructions. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 157 Note that the categories used in this section correspond to those used in Chapter 4, ÒAddressing Modes and Instruction Set Summary,Ó in The Programming Environments Manual. These categorizations are somewhat arbitrary and are MOTOROLA Chapter 6. MPC860 Instruction Set...
Page 158 (addc. addco addco.) rD,rA,rB Subtract from Carrying subfc (subfc. subfco subfco.) rD,rA,rB Add Extended adde (adde. addeo addeo.) rD,rA,rB Subtract from Extended subfe (subfe. subfeo subfeo.) rD,rA,rB Add to Minus One Extended addme (addme. addmeo addmeo.) rD,rA MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 159 L = 0. The crfD operand can be omitted if the result of the comparison is to be placed in CR0. Otherwise the target CR Þeld must be speciÞed in the instruction crfD field. MOTOROLA Chapter 6. MPC860 Instruction Set...
Page 160 GPR. See Appendix F, ÒSimplified Mnemonics,Ó in The Programming Environments Manual for a complete list of simpliÞed mnemonics that allows simpler coding of often-used functions such as clearing the leftmost or rightmost 6-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 161 ¥ Integer load and store string instructions 6.2.4.2.1 Integer Load and Store Address Generation Integer load and store operations generate effective addresses using register indirect with immediate index mode, register indirect with index mode, or register indirect mode. See MOTOROLA Chapter 6. MPC860 Instruction Set 6-11...
Page 162 Load Half Word Algebraic with Update Indexed lhaux rD,rA,rB Load Word and Zero rD,d(rA) Load Word and Zero Indexed lwzx rD,rA,rB Load Word and Zero with Update lwzu rD,d(rA) Load Word and Zero with Update Indexed lwzux rD,rA,rB 6-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 163 PowerPC system operating with little-endian byte order, these instructions have the effect of loading and storing data in big-endian order. For more information about big-endian and little-endian byte ordering, see ÒByte OrderingÓ in Chapter 3, ÒOperand Conventions,Ó in The Programming Environments Manual. MOTOROLA Chapter 6. MPC860 Instruction Set 6-13...
Page 164 Table 6-11. Integer Load and Store String Instructions Name Mnemonic Syntax Load String Word Immediate lswi rD,rA,NB Load String Word Indexed lswx rD,rA,rB Store String Word Immediate stswi rS,rA,NB Store String Word Indexed stswx rS,rA,rB 6-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 165 6.2.4.3.1 Branch Instruction Address Calculation Branch instructions can alter the sequence of instruction execution. Instruction addresses are always assumed to be word aligned; the processor ignores the two low-order bits of the generated branch target address. MOTOROLA Chapter 6. MPC860 Instruction Set 6-15...
Page 166 Condition Register NAND crnand crbD,crbA,crbB Condition Register NOR crnor crbD,crbA,crbB Condition Register Equivalent creqv crbD,crbA,crbB Condition Register AND with Complement crandc crbD,crbA,crbB Condition Register OR with Complement crorc crbD,crbA,crbB Move Condition Register Field mcrf crfD,crfS 6-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 167 See Section 8.6.6, ÒAtomic Memory References,Ó for additional information about these instructions and about related aspects of memory synchronization. Table 6-18 lists the UISA memory synchronization instructions for the MPC860. MOTOROLA Chapter 6. MPC860 Instruction Set 6-17...
Page 168 However, in reality, other processors may have read from the location during this operation. In the MPC860, the reservations are made on behalf of aligned 16-byte sections of the memory address space. 6-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 169 The PowerPC VEA describes the semantics of the memory model that can be assumed by software processes, and includes descriptions of the cache model, cache control instructions, address aliasing, and other related issues. MOTOROLA Chapter 6. MPC860 Instruction Set 6-19...
Page 170 FIFO's data. This should not be done unless it is certain that the instruction will be completed and not cancelled. The same function as eieio can be accomplished by deÞning a memory space as having the guarded attribute in the MMU, in which case, the eieio instruction is redundant. 6-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 171 The cache block could be written back as a result of the execution of an instruction that causes a cache miss and the invalid addressed cache block is the target for replacement or a Data Cache Block Store (dcbst) instruction. MOTOROLA Chapter 6. MPC860 Instruction Set 6-21...
Page 172 Table 6-15 lists the instructions provided by the MPC860 for reading from or writing to the MSR. Table 6-21. Move to/from Machine State Register Instructions Name Mnemonic Syntax Move to Machine State Register mtmsr Move from Machine State Register mfmsr 6-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 173 6.2.6.3.2 Translation Lookaside Buffer Management Instructions Refer to Chapter 9, ÒMemory Management Unit (MMU),Ó for more information about the TLB operations for the MPC860. Table 6-24 lists the TLB instructions. MOTOROLA Chapter 6. MPC860 Instruction Set 6-23...
Page 174 PowerPC architecture should not assume the existence of mnemonics not described in this document. For a complete list of simpliÞed mnemonics, see Appendix F, ÒSimpliÞed Mnemonics,Ó in The Programming Environments Manual. 6-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 175 ¥ When the exception is taken, the instruction causing the exception might not have started executing, could be partially executed, or has completed, depending on the exception and instruction types. See Table 7-20. For more information, see Section 7.1.4, ÒImplementing the Precise Exception Model.Ó MOTOROLA Chapter 7. Exceptions...
Page 176 SPR Þeld or any SPR encoded as an external SPR if SPR[0] = 1 and MSR[PR] = 1, as well as for attempts to execute supervisor-level instructions when MSR[PR] = 1. See Table 6-11. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 177 ßushed and additional instruction-related exceptions are handled in order. Typically, asynchronous exceptions are generated by signals or by other hardware conditions. Table 7-2 lists the instruction-related exceptions in the order of detection within the instruction processing. MOTOROLA Chapter 7. Exceptions...
Page 178 Signal from the interrupt controller Decrementer interrupt (masked if MSR[EE] = 0) Decrementer request 7.1.2 PowerPC-DeÞned Exceptions The following sections describe the exceptions as they are deÞned by the OEA, and describes how they are implemented on the MPC860. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 179 See Chapter 11, ÒSystem Interface Unit,Ó for more details. If MSR[ME] = 1, the machine check interrupt is taken. If SRR1[30] = 1, the interrupt is recoverable. Instruction fetching begins at offset 0x00200 and the registers are set as shown in Table 7-5. MOTOROLA Chapter 7. Exceptions...
Page 180 Þrst instruction that was discarded. If all the instructions in the completion queue were allowed to complete, execution at the end of the exception handler resumes with the next instruction. External MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 181 For lmw, stmw, lswi, lswx, stswi, and stswx instructions in little-endian mode, an alignment exception always occurs. For lmw and stmw instructions with an operand that is not aligned in big-endian mode, and for lwarx and stwcx. with an operand that is not MOTOROLA Chapter 7. Exceptions...
Page 182 Operations that are not naturally aligned may suffer performance degradation, depending on the processor design, the type of operation, the boundaries crossed, and the mode that the processor is in during execution. More speciÞcally, these operations may either cause MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 183 Note that depending on the implementation, reserved bits in the MSR may not be copied to SRR1. POW 0 Ñ Set to value of ILE Ñ Ñ When a program exception is taken, instruction execution resumes at offset 0x00700 from the physical base address indicated by MSR[IP]. MOTOROLA Chapter 7. Exceptions...
Page 184 A system call exception occurs when a System Call (sc) instruction is executed. The effective address of the instruction following the sc instruction is placed into SRR0. MSR bits are saved in SRR1, as shown in Table 7-10. Then a system call exception is generated. 7-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 185 Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI]. No change No change Copied from the ILE setting of the interrupted process Others 0 Execution resumes at offset 0x00D00 from the base address indicated by MSR[IP]. MOTOROLA Chapter 7. Exceptions 7-11...
Page 186 This type of exception occurs if MSR[IR] = 1 and an attempt is made to fetch an instruction from a page whose effective page number cannot be translated by TLB. The following registers are set: 7-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 187 OEA, the concept of segment is retained as the memory space accessible to the level-one table descriptors. ¥ The fetch access violates memory protection. ¥ The fetch access is to guarded memory. MOTOROLA Chapter 7. Exceptions 7-13...
Page 188 Set to the EA of the instruction that caused the exception. SRR1 1Ð4 10Ð15 0 Other Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI]. No change No change Copied from the ILE setting of the interrupted process Others 0 7-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 189 For L-bus breakpoint conditions. Set to the EA of the data access as computed by the instruction that caused the exception. DSISR For L-bus breakpoint conditions. Do not change. For L-bus breakpoint conditions. Do not change. MOTOROLA Chapter 7. Exceptions 7-15...
Page 190 The following instructions may cause the completion queue to Þll: ¥ Integer divide instructions ¥ Instructions that affect or use resources external to the core (load/store instructions, and especially load/store string multiple/instructions) 7-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 191 End of critical code segment in which external interrupts were disabled External interrupt disable, but other exception are recoverable: End of handlerÕs prologue, keep external nested interrupts disabled; Start of critical code segment in which external interrupts are disabled Nonrecoverable interrupt: Start of handlerÕs epilogue MOTOROLA Chapter 7. Exceptions 7-17...
Page 192 7.1.6 Exception Latency Figure 7-1 describes signiÞcant events during exception processing. ¥¥¥ Stage Fetch (in IQ) In dispatch entry (IQ0) Execute Complete (In CQ) In retirement entry (CQ0) Instruction Queue Completion Queue Figure 7-1. Exception Latency 7-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 193 MOTOROLA Chapter 7. Exceptions 7-19...
Page 194 Debug I- breakpoint Before Faulting instruction Debug L- breakpoint Load/store After Faulting instruction + 4 Software emulation Before Faulting instruction Floating-point unavailable Floating-point Before Faulting instruction Implementation-speciÞc exceptions not deÞned by the PowerPC architecture 7-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 195 ¥ Individual cache blocks can be locked so that frequently accessed instructions and/or data are guaranteed to be resident in the respective cache. On a cache miss, the MPC860Õs cache blocks are Þlled in 16-byte bursts. The burst Þll is MOTOROLA Chapter 8. Instruction and Data Caches...
Page 196 8.1 Instruction Cache Organization The MPC860 instruction cache is organized as 128 sets of two blocks, as shown in Figure 8-1. Each block consists of 16 bytes, a single state bit, a lock bit, and an address tag. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 197 A[21Ð27] provide the index to select a set, and bits A[28Ð29] select a word within a block. The tags consist of the high-order physical address bits PA[0Ð20]. Address translation occurs in parallel with set selection (from A[21Ð27]). MOTOROLA Chapter 8. Instruction and Data Caches...
Page 198 The MPC860 supports commands for locking and unlocking individual cache blocks and for unlocking all the cache blocks at once. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 199 Each cache block contains four contiguous words from memory that are loaded from a four-word boundary (that is, bits A[28Ð31] of the logical (effective) addresses are zero); as a result, cache blocks are aligned with page boundaries. Note that address bits A[21Ð27] MOTOROLA Chapter 8. Instruction and Data Caches...
Page 200 (that is, when MSR[PR] = 0). Any attempt to access these SPRs with a user-level program (MSR[PR] = 1) results in a supervisor-level program exception. The IC_CST register, shown in Figure 8-3, has an SPR encoding of 560. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 201 Error detected Note that this is a read-only, sticky bit, set only by the MPC860 when an error is detected. Reading this bit clears it. CCER3 Instruction cache error type 3Ñreserved. 13Ð31 Ñ Reserved MOTOROLA Chapter 8. Instruction and Data Caches...
Page 202 The instruction cache read command, issued by reading the IC_DAT register, uses the IC_ADR register to qualify what is to be read. Table 8-4 describes the Þelds of the IC_ADR register during an instruction cache read command. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 203 When disabled, the MPC860 ignores the instruction cache valid bit and operates as if all accesses have caching-inhibited access attributes (that is, all instruction fetches are propagated to the bus as single-beat transactions). Disabling the instruction cache does not MOTOROLA Chapter 8. Instruction and Data Caches...
Page 204 Note that the MPC860 considers all zero-wait-state devices on the internal bus as caching-inhibited. For this reason, software should not perform load & lock cache block operations from these devices on the internal bus. 8-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 205 ÒByte Ordering,Ó for more information. The mtspr and mfspr instructions are used to access the cache control registers, but they can be accessed only by supervisor-level programs (that is, when MSR[PR] = 0). Any MOTOROLA Chapter 8. Instruction and Data Caches 8-11...
Page 206 See Appendix A, ÒByte Ordering,Ó for more information on MPC860 byte ordering. Note that this is a read-only bit. Any attempt to write to it is ignored. This bit is programmed by issuing the appropriate command in DC_CST[CMD]. Reserved 8-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 207 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FIELD RESET Ñ Figure 8-7. Data Cache Address Register (DC_ADR) MOTOROLA Chapter 8. Instruction and Data Caches 8-13...
Page 208 Table 8-9. DC_ADR Fields for Cache Read Commands 0Ð17 21Ð27 28Ð31 Reserved 0 Tags 0 Way 0 Reserved Set select Reserved 1 Way 1 (0Ð127) 1 Copyback Reserved Copyback buffer Reserved buffer address/ data-word select 8-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 209 & lock cache block and ßush cache block commands. Note that when the data cache is executing a command, it stops handling CPU requests, which can result in machine stalls. MOTOROLA Chapter 8. Instruction and Data Caches 8-15...
Page 210 These bits are set by the MPC860 and are cleared by software. Note that the MPC860 considers all zero-wait-state devices on the internal bus as caching-inhibited. For this reason, software should not perform load & lock operations from these devices on the internal bus. 8-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 211 DC_CST[CCER1] is set and a machine check exception is generated. The data of the cache block ßagged by the bus error is contained in the copyback buffer; it will have already been MOTOROLA Chapter 8. Instruction and Data Caches 8-17...
Page 212 The MPC860 treats these instructions identically (that is, a dcbtst instruction behaves exactly the same as a dcbt instruction on the MPC860). 8-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 213 ÒReading Data Cache Tags and Copyback Buffer,Ó for more information. The function of this instruction is independent of the memory/cache access attributes. The dcbst instruction executes regardless of whether the cache is disabled or the cache block is locked. MOTOROLA Chapter 8. Instruction and Data Caches 8-19...
Page 214 PowerPC core. As shown in Figure 8-1, bits 21Ð27 of the instruction address provide the index to select a set (0Ð127) within the instruction cache array. The tags from both ways of the set are compared against bits 0Ð20 of the instruction address. If a 8-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 215 To minimize power consumption, the MPC860 can detect that one of the buffers contains the requested instruction and service the instruction request from the buffers without activating the instruction cache array. MOTOROLA Chapter 8. Instruction and Data Caches 8-21...
Page 216 Locked cache blocks are never replaced. The instruction cache is not blocked to internal accesses while the fetch (caused by a cache miss) completes. This functionality is sometimes referred to as Ôhits under misses,Õ because 8-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 217 MOTOROLA Chapter 8. Instruction and Data Caches 8-23...
Page 218 Therefore, software must maintain data cache coherency. The MPC860 does not provide support for snooping external bus activity. All coherency between the internal caches and external agents (memory or I/O devices) must be controlled by 8-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 219 Þll is waiting to complete. If no bus errors are encountered during the 4-word cache block load, the burst buffer is written to the cache array (provided the cache array is not busy servicing a hit) and the cache block is marked unmodiÞed-valid. MOTOROLA Chapter 8. Instruction and Data Caches 8-25...
Page 220 If the store hit is to a unmodiÞed-valid cache block, then data is stored in the cache block and the block is marked modiÞed-valid. In either case, the LRU state of the set is updated to reßect the hit. 8-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 221 The PowerPC architecture allows the result of such programming errors to be boundedly undeÞned. Software must ensure that data from a caching-inhibited regions have not been previously loaded into the data cache, or, if they MOTOROLA Chapter 8. Instruction and Data Caches 8-27...
Page 222 If a memory region is marked caching-allowed, the MPC860 assumes that it is the single master in the system to that region. If a caching-allowed lwarx or stwcx. access misses in the data cache, the transaction on the internal and external buses do not have a reservation. 8-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 223 8.8.1 Instruction and Data Cache Operation in Debug Mode The development system interface of the MPC860 uses the development port, which is a dedicated serial port. The development port is a relatively inexpensive interface that allows MOTOROLA Chapter 8. Instruction and Data Caches 8-29...
Page 224 4. To restore the old state of the LRU bits make sure that the last access (load& lock cache block or unlock cache block command) is performed on the most-recently used way (not the LRU way). 8-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 225 For the dcbst/dcbf/dcbi instructions, the data cache and memory are updated according to the PowerPC architecture, but the LRU bits in the data cache array are not updated. MOTOROLA Chapter 8. Instruction and Data Caches 8-31...
Page 226 Part II. PowerPC Microprocessor Module 8-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 227 Ñ Guarded attribute for memory-mapped I/O and other nonspeculative regions ¥ Instruction and data address translation can be disabled separately. ¥ MPC860-speciÞc special-purpose registers (SPRs) accessible with the PowerPC mfspr/mtspr instructions. MOTOROLA Chapter 9. Memory Management Unit (MMU)
Page 228 Ñ Additional registers and exceptions for handling table walks in software. Note that although the MPC860 does not deÞne segment registers as they are deÞned by the OEA, the concept of segment is retained as the memory space accessible to the level-one table descriptors. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 229 (EPN) overlaps one in the TLB (when taking into account pages sizes, subpage validity ßags, user/supervisor state, address pace ID (ASID), and the SH values of the TLB entries), the new EPN is written and the old one is invalidated. MOTOROLA Chapter 9. Memory Management Unit (MMU)
Page 230 DMMU does not implement a fast TLB mechanism. The DTLB is accessed for each transfer simultaneously with the data cache tag read, hence there is no time penalty. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 231 CASID are provided to the TLB, as shown in Figure 9-3. In the TLB, the EA and CASID are compared with each entryÕs EPN and ASID. The CASID is compared only when the matching entry is programmed as unshared. See Table 9-11 and Table 9-12. MOTOROLA Chapter 9. Memory Management Unit (MMU)
Page 232 Mx_AP Þelds to 01. In PowerPC mode, each Þeld holds the Kp and Ks bits for the corresponding segment deÞned by the level-one table descriptor. In domain manager mode, each Þeld holds override information over the page protection settingÑno override, no access override, and free access override. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 233 4-Kbyte pages differ. ¥ Mode 3ÑProtection resolution to 1-Kbyte minimum subpage size, with no restriction on subpage mapping. In this mode, set: Ñ MD_CTR[TWAM] = 0 Ñ Mx_CTR[PPM] = 0 Ñ Mx_CTR[PPC5] = 0 MOTOROLA Chapter 9. Memory Management Unit (MMU)
Page 234 Therefore, attempting to write to a page marked unmodiÞed invalidates that entry and causes an implementation-speciÞc DTLB error exception. If change bits are not needed, set the C bit to one by default in the PTEs. MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 235 9.7 Translation Table Structure The MMU hardware supports a two-level software tablewalk. Other table structures are not precluded. Figure 9-4 shows the two-level translation table when MD_CTR[TWAM] = 1 (4-Kbyte resolution of protection). MOTOROLA Chapter 9. Memory Management Unit (MMU)
Page 236 M_TWB. EA[0Ð9] indicates the level-one page descriptor. As shown in Table 9-1, an 8-Mbyte page requires two identical entries in the level-one table, one for bit 9 = 0 and one for bit 9 = 1. 9-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 237 10Ð19 to Þnd the level-two page descriptor. For pages larger than 4 Kbytes, the entry in the level-two table must be duplicated according to page size, as shown in Table 9-1. MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-11...
Page 238 M_TWB. The level-one table is indexed by EA[0Ð11] to get the level-one page descriptor. For 8-Mbyte pages, there must be eight identical entries in the level-one table for EA[9Ð11]. 9-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 239 11 8 Kbyte 10 Reserved Writethrough attribute for entry 0 Copyback cache policy region (default) 1 Writethrough cache policy region Level-one segment valid bit 0 Segment is not valid 1 Segment is valid MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-13...
Page 240 The PowerPC tlbie and tlbia instructions can be used to invalidate TLBs. MMU registers should be accessed when both MSR[IR] = 0 and MSR[DR] = 0. No similar restriction exists for tlbie and tlbia. 9-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 241 9.8.12.2 MI_RAM1 IMMU RAM entry read register 1 9.8.12.3 MD_CAM DMMU CAM entry read register 9.8.12.4 MD_RAM0 DMMU RAM entry read register 0 9.8.12.5 MD_RAM1 DMMU RAM entry read register 1 9.8.13 MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-15...
Page 242 Reserved. Ignored on write. Returns 0 on read. 19Ð23 ITLB_INDX ITLB index. Points to the ITLB entry to be loaded. Decremented every ITLB update 24Ð31 Ñ Reserved. Ignored on write. Returns 0 on read. 9-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 243 Reserved. Ignored on write. Returns 0 on read 19Ð23 DTLB_INDX DTLB index. Points to DTLB entry to be loaded. Decremented every DTLB update. 24Ð31 Ñ Reserved. Ignored on write. Returns 0 on read MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-17...
Page 244 M_CASID on a TLB miss. 9.8.4 IMMU Tablewalk Control Register (MI_TWC) The IMMU tablewalk control register (MI_TWC), shown in Figure 9-9, contains the access protection group and page size of the entry to be loaded into the TLB. 9-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 245 9.8.5 DMMU Tablewalk Control Register (MD_TWC) The DMMU tablewalk control register (MD_TWC), shown in Figure 9-10, contains the level-two pointer and access protection group of an entry to be loaded into the TLB. MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-19...
Page 246 The IMMU real page number register (MI_RPN), shown in Figure 9-11, contains the physical address and the memory attributes of an entry to be loaded into a TLB. MI_RPN should be written after MI_EPN and MI_TWC are written. 9-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 247 0 This entry matches only if ASID Þeld in the TLB entry matches the value M_CASID. 1 ASID comparison is disabled for the entry. Cache-inhibit attribute for the entry. Entry valid indication. MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-21...
Page 248 0100 Hit only for user accesses Resolution ModesÓ). Otherwise, set 1100 Hit for both to 0b1111. Small page size: Clear. Small page size. Valid only when L1 descriptor[PS] = 00 0 4 Kbyte 1 16 Kbyte 9-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 249 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field Ñ CASID Reset Ñ Figure 9-14. MMU Current Address Space ID Register (M_CASID) MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-23...
Page 250 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reset Ñ Figure 9-16. MMU Tablewalk Special Register (M_TW) 9-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 251 Address space ID of the DTLB entry to be compared with M_CASID[CASID] Shared page 0 This entry matches only if the ASID Þeld in the DTLB entry matches the value in M_CASID. 1 ASID comparison is disabled for the entry MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-25...
Page 252 20Ð22 PS_B Page size. (Values not shown are reserved) 000 4 Kbyte 001 16 Kbyte 011 512 Kbyte 111 8 Mbyte Cache-inhibit attribute for the entry 24Ð27 APG Access protection group. Up to 16 protection groups supported (uses oneÕs complement format) 9-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 253 0 Subpage 2 (Address[20Ð21] = 10) User fetch is not permitted 1 Subpage 2 (Address[20Ð21] = 10) User fetch is permitted 0 Subpage 3 (Address[20Ð21] = 11) User fetch is not permitted 1 Subpage 3 (Address[20Ð21] = 11) User fetch is permitted MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-27...
Page 254 0 Subpage 2 (address[20Ð21] = 10) is not valid 1 Subpage 2 (address[20Ð21] = 10) is valid 0 Subpage 3 (address[20Ð21] = 11) is not valid 1 Subpage 3 (address[20Ð21] = 11) is valid 9-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 255 011 512 Kbyte 111 8 Mbyte 23Ð26 APGI Access protection group inverted. Access protection group number in oneÕs complement format Guarded memory attribute for the entry 0 Nonguarded memory 1 Guarded memory MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-29...
Page 256 Software should take an appropriate action before setting this bit to 1. 1 Changed region. Write access is allowed to this page. Entry valid ßag 0 Entry is invalid 1 Entry is valid 9-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 257 1 Subpage 3 (address[20Ð21] = 11) User read access is permitted UWP3 0 Subpage 3 (address[20Ð21] = 11) User write access is not permitted 1 Subpage 3 (address[20Ð21] = 11) User write access is permitted MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-31...
Page 258 ¥ The level-two pointer is generated when an mfspr[MD_TWC] is performed by concatenating the level-two table base (extracted from the level-one table) with the level-two index. 9-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 259 9.10.2 Locking TLB Entries Four entries in each TLB can be made unavailable to the replacement algorithm, thus enabling the user to lock translation entries into them by specially conÞguring the TLB replacement counters. MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-33...
Page 260 The ASID value in the entry is ignored for the purpose of matching an invalidate address, thus multiple entries can be invalidated if they have the same effective address and different ASID values. 9-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 261 MI_CTR[ITLB_INDX], negating MD_EPN[EV] or MI_EPN[EV], and writing to the appropriate MD_RPN or MI_RPN. The TLBs are not invalidated automatically on reset, but are disabled. However, they must be invalidated under program control during initialization. MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-35...
Page 262 Part II. PowerPC Microprocessor Module 9-36 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 263 The example in Section 10.1.3, ÒPrivate Writeback Bus Load,Ó has no such dependency. r12,64 (SP) r3,r12,3 addic r4,r14,1 mulli r5,r3,3 addi r4,3(r0) MOTOROLA Chapter 10. Instruction Execution Timing 10-1...
Page 264 GCLK1 Fetch mulli addic Decode mulli addic Read + Execute mulli sub, mulli addic addic Writeback mulli Figure 10-3. Writeback Arbitration TimingÑExample 2 10-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 265 GCLK1 Fetch addic Decode Read + Execute Bubble Bubble Bubble Bubble Writeback L Address Drive L Data Cache Address Load Writeback E Address E Data Figure 10-5. External Load Timing MOTOROLA Chapter 10. Instruction Execution Timing 10-3...
Page 266 BPU allows the two bubbles caused by the bl issue and execution to overlap the two bubbles caused by the load. Issuing bl causes a bubble because it does no work. r12,64 (SP) r3,r12,3 addic r4,r14,1 func func: mulli r5,r3,3 addi r4,3(r0) 10-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 267 Decode cmpi addic mulli Read + Execute Bubble Bubble cmpi addic mulli Writeback addic L Address Drive L Data Load Writeback Branch Decode Branch Execute Branch Final Decision Figure 10-8. Branch Prediction Timing MOTOROLA Chapter 10. Instruction Execution Timing 10-5...
Page 268 Integer store: stb, stbu, stbx, stbux, sth, sthu, sthx, sthux, stw, stwu, stwbrx, stwx, stwux, sthbrx Integer load/store multiple: lmw, smw Serialize + 1 + no. of registers LSU Synchronize: sync Serialize + 1 10-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 269 1 cycle 1 cycle 2 cycles 5 cycles Load/store multiple 1 + N 1 + N æ ö æ ö -------------- -------------- è ø è ø N denotes the number of registers transferred. MOTOROLA Chapter 10. Instruction Execution Timing 10-7...
Page 270 See Section 5.1.3.1, ÒAccessing SPRs.Ó If the access ends in a bus error, a software emulation exception is taken. All write operations to off-core SPRs (mtspr) are previously synchronized. In other words, the instruction is not taken until all prior instructions terminate. 10-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 271 ¥ Chapter 12, ÒReset,Ó describes the behavior of the MPC860 at reset and start-up. Suggested Reading Supporting documentation for the MPC860 can be accessed through the world-wide web at http://www.motorola.com/SPS/RISC/netcomm and at http://www.mot.com/SPS/ PowerPC/. This documentation includes technical speciÞcations, reference materials, and detailed applications notes.
Page 272 Decrementer register Direct memory access DRAM Dynamic random access memory DTLB Data translation lookaside buffer Effective address General-purpose register IEEE Institute of Electrical and Electronics Engineers ITLB Instruction translation lookaside buffer Least-signiÞcant byte Least-signiÞcant bit III-ii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 273 Meaning Load/store unit Memory management unit Most-signiÞcant byte Most-signiÞcant bit Machine state register Peripheral component interconnect RISC Reduced instruction set computing RTOS Real-time operating system Receive Special-purpose register Time base register Translation lookaside buffer Transmit MOTOROLA Part III. Configuration III-iii...
Page 274 Part III. Configuration III-iv MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 275 PCMCIA sockets with a maximum of eight memory or I/O windows. 11.1 Features The following is a list of the SIUÕs main features: ¥ System conÞguration and protection ¥ System interrupt conÞguration ¥ System reset monitoring and generation ¥ Clock synthesizer MOTOROLA Chapter 11. System Interface Unit 11-1...
Page 276 The associated bit in the timebase status and control register (TBSCR) is set for the reference register that generated the interrupt. The timebase is clocked by the TMBCLK clock. 11-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 277 11.3 Multiplexing SIU Pins Due to the limited number of pins available in the MPC860 package, some of the functionalities share pins. Table 11-1 shows how the functionality is controlled on each pin. MOTOROLA Chapter 11. System Interface Unit 11-3...
Page 278 Using mfspr, software can read IMMR to determine the location and availability of any on-chip system resource. ISB can be written by mtspr, but PARTNUM and MASKNUM are mask programmed and cannot be changed. 11-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 279 MPC860. Intended to help factory test and user code that is sensitive to part reÞnements. For the latest documentation on part/revision numbers and microcode REV_NUMs, see the website at http://www.motorola.com/SPS/RISC/netcomm/. 11.4.2 SIU Module ConÞguration Register (SIUMCR) The SIU module conÞguration register (SIUMCR) contains bits that conÞgure the following features in the SIU: ¥...
Page 280 Hardware SpeciÞcations for more information.) This bit is locked by the DLK bit. 0 Disable show cycles for all internal data cycles. 1 Show address and data of all internal data cycles. 11-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 281 11 ALE_B/DSCK/AT1 functions as DSCK IP_B6/DSDI/AT0 functions as DSDI OP3/MODCK2/DSDO functions as DSDO IP_B7/PTR/AT3 functions as PTR TCK/DSCK functions as TCK TDI/DSDI functions as TDI TDO/DSDO functions as TDO Ñ Reserved, should be cleared. MOTOROLA Chapter 11. System Interface Unit 11-7...
Page 282 Bank 2 double drive. If this bit is set, CS2 is reßected on GPL_x2. B3DD Bank 3 double drive. If this bit is set, CS3 is reßected on GPL_x3. 28Ð31 Ñ Reserved, should be cleared. 11-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 283 0 The software watchdog timer causes an NMI (system reset interrupt) to the core. 1 The software watchdog timer causes an HRESET (default). Software watchdog prescale. 0 The software watchdog timer is not prescaled. 1 The software watchdog timer is prescaled by a factor of 2,048. MOTOROLA Chapter 11. System Interface Unit 11-9...
Page 284 28Ð31 DPB[0Ð3] Data parity error on bytes 0Ð3. Each byte lane has four parity error status bits; one is set for the byte that had a parity error when an internal master requested a data load. Parity checking for memory not controlled by the memory controller is enabled by SIUMCR[PNCS], see Table 11-3. 11-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 285 (including reads or writes of any other value) to a key register will lock its associated SIU register. For example, writing a 0x55CCAA33 to the RTCK key register allows the RTC register to be written. The key registers are write-only; a read of the MOTOROLA Chapter 11. System Interface Unit 11-11...
Page 286 Module ConÞguration Register (SIUMCR).Ó 11.5.1 Interrupt Structure The SIU receives interrupts from internal sources, like the PIT, real-time clock, communications processor module (CPM), and the external IRQ pins. Figure 11-7 shows the MPC860 interrupt structure. 11-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 287 Chapter 35, ÒCPM Interrupt Controller.Ó Section 11.5.3.1, ÒNonmaskable InterruptsÑIRQ0 and SWT,Ó describes how IRQ0 operates differently from other IRQ signals, and how the operation is conÞgurable through SIU registers. MOTOROLA Chapter 11. System Interface Unit 11-13...
Page 288 IRQ3 0001_1000 Internal Level 3 0001_1100 IRQ4 0010_0000 Internal Level 4 0010_0100 IRQ5 0010_1000 Internal Level 5 0010_1100 IRQ6 0011_0000 Internal Level 6 0011_0100 IRQ7 0011_1000 Lowest Internal Level 7 0011_1100 16-31 Reserved Ñ 11-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 289 Figure 11-9 is a logical representation of IRQ0. SIEL[ED0] SIEL[ED0] Level Level IRQ0 Edge Edge SIPEND[IRQ0] SIPEND[IRQ0] Figure 11-9. IRQ0 Logical Representation Table 11-8 describes the differences between IRQ0 and other IRQ interrupts. MOTOROLA Chapter 11. System Interface Unit 11-15...
Page 290 ¥ If an IRQ pin is deÞned as an edge interrupt, the corresponding bit being set indicates that a falling edge was detected on the line. These bits are reset by writing ones to them. 11-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 291 Field LVM3 IRM LVM4 IRM LVM6 IRM LVM7 Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x014 Field Ñ Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x016 Figure 11-11. SIU Interrupt Mask Register (SIMASK) MOTOROLA Chapter 11. System Interface Unit 11-17...
Page 292 ED0 WM0 ED1 WM1 ED2 WM2 ED3 WM3 ED4 WM4 ED5 WM5 ED6 WM6 ED7 WM7 Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x018 Field Ñ Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x018 Figure 11-12. SIU Interrupt Edge/Level Register (SIEL) 11-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 293 (branch). The interrupt code is the interrupt number times 4, which allows indexing into the table. When read as a half word, each entry can contain a full routine of up to 256 instructions; see Figure 11-14 and Table 11-7. MOTOROLA Chapter 11. System Interface Unit 11-19...
Page 294 (TS), the monitor begins counting and stops when transfer acknowledge (TA), retry (RETRY) or transfer error (TEA) is asserted. For burst cycles, this action is also performed between subsequent TA assertions for each data beat. If the monitor times out, 11-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 295 16-bit down-counter clocked by the system clock. When necessary, an additional divide by 2,048 prescaler is used. After the timer reaches 0x0, a software watchdog expiration request is issued to the reset or NMI control logic. At reset, MOTOROLA Chapter 11. System Interface Unit 11-21...
Page 296 0xAA39 should be written to this register. The SWSR can be written at any time, but returns all zeros when read. Field Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x00E Figure 11-17. Software Service Register (SWSR) 11-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 297 Control of the decrementer is provided in the TBSCR. The decrementer and timebase use TMBCLK. Note that DEC is a keyed register. It must be unlocked in TBK before it can be written. MOTOROLA Chapter 11. System Interface Unit 11-23...
Page 298 Figure 11-19 shows TBU. Note that the TBU and TBL are keyed registers. They must be unlocked in TBK before they can be written. É Field Reset Ñ 269 (Read)/285 (Write) Figure 11-19. Timebase Upper Register (TBU) 11-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 299 TBREFA (IMMR & 0xFFFF0000) + 0x204/TBREFB (IMMR & 0xFFFF0000) + 0x208 Field TBREFA/TBREFB Reset Ñ Addr TBREFA (IMMR & 0xFFFF0000) + 0x206/TBREFB (IMMR & 0xFFFF0000) + 0x20A Figure 11-21. Timebase Reference Registers (TBREFA and TBREFB) MOTOROLA Chapter 11. System Interface Unit 11-25...
Page 300 REFBE Timebase freeze enable 0 The timebase and decrementer are unaffected. 1 The FRZ signal stops the timebase and decrementer. Timebase enable 0 Disables timebase and decrementer operation. 1 Enables timebase and decrementer operation. 11-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 301 RTCSC is a keyed register. It must be unlocked in RTCSCK before it can be written. Field RTCIRQ SEC ALR Ñ RTF RTE Reset 0000_0000 Ñ Ñ Addr (IMMR & 0xFFFF0000) + 0x220 Figure 11-24. Real-Time Clock Status and Control Register (RTCSC) Table 11-20 describes RTCSC Þelds. MOTOROLA Chapter 11. System Interface Unit 11-27...
Page 302 (IMMR & 0xFFFF0000) + 0x226 Figure 11-25. Real-Time Clock Register (RTC) Table 11-21 describes the RTC. Table 11-21. RTC Field Description Bits Name Description 0Ð31 RTC Real-time clock. Represents time measured in seconds. Each unit represents one second. 11-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 303 MHz/512 or 32.768 KHz/4). RTSEC resets at 8192 and increments RTC. Thus, RTC contains the time in seconds and RTSEC functions as a divider. For a 38.4-KHz crystal (instead of 32.768 KHz), RTCSC[38K] should be set to make RTSEC reset at 9600 instead of 8192. 11-29 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 304 PITC. If the PTE bit is not set, the PIT is unable to count and retains the old count value. Reading the PIT does not affect it. 11-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 305 Note that PISCR is a keyed register. It must be unlocked in PISCRK before it can be written. Field PIRQ Ñ PIE PITF PTE Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x240 Figure 11-29. Periodic Interrupt Status and Control Register (PISCR) MOTOROLA Chapter 11. System Interface Unit 11-31...
Page 306 Table 11-25 describes PITC Þelds. Table 11-25. PITC Field Descriptions Bits Name Description 0Ð15 PITC PIT count. Contains the count for the periodic timer. Setting this Þeld to 0xFFFF selects the maximum count period. 11-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 307 This is controlled by the associated bits in the control register of each timer. If they are programmed to stop counting when FRZ is asserted, the counters maintain their values until FRZ is negated. The bus monitor, however, will be enabled regardless of this signalÕs state. MOTOROLA Chapter 11. System Interface Unit 11-33...
Page 308 The PIT, decrementer, and timebase are not inßuenced by these low-power modes and they continue to run at their respective frequencies. These timers can generate an interrupt to bring the MPC860 out of the low-power modes. 11-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 309 The MPC860 has several sources of input to the reset logic: ¥ Power-on reset ¥ External hard reset ¥ Internal hard reset Ñ Loss of lock Ñ Software watchdog reset Ñ Checkstop reset Ñ Debug port hard reset ¥ JTAG reset MOTOROLA Chapter 12. Reset 12-1...
Page 310 HRESET and SRESET signals. Following the negation of HRESET and SRESET a 16-cycle period passes before an external hard or soft reset will be sampled. Note that external pull-up resistors should be provided to drive the 12-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 311 See Section 37.3.2.1.2, ÒDevelopment Serial Data In (DSDI).Ó 12.1.5 JTAG Reset When the JTAG logic asserts the JTAG reset signal, an internal soft reset sequence will be generated. MOTOROLA Chapter 12. Reset 12-3...
Page 312 SRESET signal. After 512 cycles the core negates the SRESET signal and the debug port conÞguration is sampled from the DSDI and DSCK signals. Once the core negates SRESET 16 clock cycles must elapse before the external soft reset signal is sampled. 12-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 313 Figure 12-3. Reset Status Register (RSR) The RSR bits are described in Table 12-2. Note that the bits in this register (except those that are reserved) are negated by writing 1; writing 0 has no effect. MOTOROLA Chapter 12. Reset 12-5...
Page 314 MPC860 using hard and soft reset events. 12.3.1 Hard Reset When a hard reset event occurs, the MPC860 determines its initial mode of operation by sampling the values present on the data bus (D[0Ð31]) or from an internal default constant 12-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 315 Figure 12-5 shows a reset operation with a short PORESET signal assertion. Note that the conÞguration of the MPC860 is determined from the signal levels driven on the D[0Ð31] signals following the assertion of RSTCONF and the negation of HRESET. MOTOROLA Chapter 12. Reset 12-7...
Page 316 Figure 12-5. Reset Configuration Sampling for Short PORESET Assertion Figure 12-6 shows a reset operation with a long PORESET signal assertion. CLKOUT PORESET INTPORESET HRESET RSTCONF TSUP D[0:31] Default RSTCONF Controlled Figure 12-6. Reset Configuration Sampling for Long PORESET Assertion 12-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 317 IIP is cleared (default), the MSR[IP] initial value is one; if it is set to one, the MSR[IP] initial value is zero. See Section 5.1.2.3.1, ÒMachine State Register (MSR).Ó 2Ð3 Ñ Reserved for future use and should be allowed to ßoat. MOTOROLA Chapter 12. Reset 12-9...
Page 318 IP_B3/IWP2/VF2 functions as VF2 IP_B4/LWP0/VF0 functions as VF0 IP_B5/LWP1/VF1 functions as VF1 OP2/MODCK1/STS functions as STS ALE_B/DSCK/AT1 functions as AT1 IP_B2/AT2 functions as AT2 IP_B6/DSDI/AT0 functions as AT0 IP_B7/PTR/AT3 functions as AT3 OP3/MODCK2/DSDO functions as OP3 12-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 319 Reserved. This bit is reserved for future use and should be allowed to ßoat. 12.3.2 Soft Reset When a soft reset event occurs, the MPC860 reconÞgures the development port. See Section 37.3.1.2, ÒEntering Debug Mode,Ó and Section 37.3.2.3.3, ÒSelection of Development Port Clock Mode.Ó MOTOROLA Chapter 12. Reset 12-11...
Page 320 Part III. Configuration 12-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 321 (GPCM) and a pair of user-programmable machines (UPMs). ¥ Chapter 17, ÒPCMCIA Interface,Ó describes the PCMCIA host adapter module, which provides all control logic for a PCMCIA socket interface and requires only additional external analog power switching logic and buffering. MOTOROLA Part IV. Hardware Interface IV-i...
Page 322 The PowerPC documentation is organized in the following types of documents: ¥ PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors (Motorola order #: MPCBUSIF/AD) provides a detailed functional description of the 60x bus interface, as implemented on the PowerPC 601ª, 603, and 604 family of PowerPC microprocessors.
Page 323 High-level data link control Inter-integrated circuit Inter-chip digital link IEEE Institute of Electrical and Electronics Engineers IrDA Infrared Data Association ISDN Integrated services digital network JTAG Joint Test Action Group LIFO Last-in-Þrst-out Least recently used Least-signiÞcant byte MOTOROLA Part IV. Hardware Interface IV-iii...
Page 324 Systems network architecture. Serial peripheral interface Special-purpose register SRAM Static random access memory Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UISA User instruction set architecture User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter IV-iv MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 325 Part IV. Hardware Interface MOTOROLA Part IV. Hardware Interface IV-v...
Page 326 Part IV. Hardware Interface IV-vi MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 327 Chapter 13 External Signals This chapter contains descriptions of the MPC860 input and output signals, showing multiplexing, pin assignments, and reset values. Figure 13-1 shows the signals grouped by function. MOTOROLA Chapter 13. External Signals 13-1...
Page 328 ALE_B/DSCK/AT1 RxD4/PD9 WAIT_B TxD4/PD8 IP_B[0Ð1]/WP[0Ð1]/VFLS[0Ð1] RTS3/PD7 IP_B2/IOIS16_B /AT2 RTS4/PD6 IP_B3/WP2/VF2 REJECT2 /PD5 IP_B4/LWP0/VF0 REJECT3 /PD4 IP_B5/LWP1/VF1 REJECT4 /PD3 IP_B6/DSDI/AT0 IP_B7/PTR/VAT3 DSDI/TDI OP[0Ð1] DSCK/TCK OP2/MODCK1/STS TRST OP3/MODCK2/DSDO DSDO/TDO BADDR30/REG BADDR[28Ð29] Figure 13-1. MPC860 External Signals 13-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 329 1ÐV17 TxD4/PD8 1ÐW17 RTS3/PD7 1ÐT15 RTS4/PD6 1ÐV16 REJECT2 /PD5 1ÐU15 REJECT3 /PD4 1ÐU16 REJECT4 /PD3 1ÐW16 1ÐG18 DSDI/TDI 1ÐH17 DSCK/TCK 1ÐH16 TRST 1ÐG19 DSDO/TDO 1ÐG17 1ÐL3 Figure 13-2. Signals and Pin Numbers (Part 1) MOTOROLA Chapter 13. External Signals 13-3...
Page 330 R4Ð1 IP_B[0Ð1]/WP[0Ð1]/VFLS[0Ð1] H2, J3Ð2 J2Ð1 IP_B2/IOIS16_B /AT2 G1Ð1 IP_B3/WP2/VF2 G2Ð1 IP_B4/LWP0/VF0 J4Ð1 IP_B5/LWP1/VF1 K3Ð1 IP_B6/DSDI/AT0 H1Ð1 IP_B7/PTR/VAT3 L4, L2Ð2 OP[0Ð1] L1Ð1 OP2/MODCK1/STS M4Ð1 OP3/MODCK2/DSDO BADDR30/REG BADDR[28Ð29] Figure 13-3. Signals and Pin Numbers (Part 2) 13-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 331 The MPC860 samples TS when it is not the external bus master to allow the memory controller/PCMCIA interface to control the accessed slave device. It indicates that an external synchronous master initiated a transaction. MOTOROLA Chapter 13. External Signals 13-5...
Page 332 (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of CR/IRQ3 (if deÞned as IRQ3) and DP0/IRQ3 if deÞned as IRQ3. 13-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 333 (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of this line (if deÞned as IRQ6) and the FRZ/IRQ6 (if deÞned as IRQ6). MOTOROLA Chapter 13. External Signals 13-7...
Page 334 BR7 and OR7 in the memory controller. Card Enable 2 Slot BÑThis output enables odd byte transfers when accesses to the PCMCIA Slot B are handled under the control of the PCMCIA interface. 13-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 335 UPMB, as programmed by the user. For read or writes, asserted only if their corresponding data lanes contain valid data: BS_A0 for D[0Ð7], BS_A1 for D[8Ð15], BS_A2 for D[16Ð23], BS_A3 for D[24Ð31] MOTOROLA Chapter 13. External Signals 13-9...
Page 336 When RSTCONF is negated, the MPC860 uses the default conÞguration mode. Note that the initial base address of internal registers is determined in this sequence. 13-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 337 I/O region in socket A of the PCMCIA space. IP_A[3Ð7] Hi-Z W2, U4, U5, Input Input Port A 3-7ÑThe MPC860 monitors these inputs; their T6, T3 values and changes are reported in the PIPR and PSCR of the PCMCIA interface. MOTOROLA Chapter 13. External Signals 13-11...
Page 338 ßow executed by the core. Visible Instruction Queue Flushes StatusÑThe MPC860 outputs VF0 with VF1/VF2 when instruction ßow tracking is required. VFn reports the number of instructions ßushed from the instruction queue in the core. 13-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 339 PGCRB register in the PCMCIA DSDO interface. Mode Clock 2ÑThis input is sampled at the PORESET negation to conÞgure the PLL/clock mode of operation. Development Serial Data OutputÑOutput data from the debug port interface. MOTOROLA Chapter 13. External Signals 13-13...
Page 340 PA[11] Hi-Z Bidirectional General-Purpose I/O Port A Bit 11ÑBit 11 of the L1TXDB (Optional: general-purpose I/O port A. RXD3 Open-drain) L1TXDBÑTransmit data output for the serial interface TDMb. RXD3 ÑReceive data input for SCC3. 13-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 341 CLK6ÑOne of eight clock inputs that can be used to clock the L1RCLKB SCCs and SMCs. BRGCLK2 TOUT3ÑTimer 3 output. L1RCLKBÑReceive clock for the serial interface TDMb. BRGCLK2ÑOne of the two external clock inputs of the BRGs. MOTOROLA Chapter 13. External Signals 13-15...
Page 342 SMTXD1 (Optional: general-purpose I/O port B. Open-drain) SMTXD1ÑSMC1 transmit data output. PB[24] Hi-Z Bidirectional General-Purpose I/O Port B Bit 24ÑBit 24 of the SMRXD1 (Optional: general-purpose I/O port B. Open-drain) SMRXD1ÑSMC1 receive data input. 13-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 343 I/O port B. BRGO3ÑBRG3 output clock. PB[14] Hi-Z Bidirectional General-Purpose I/O Port B Bit 14ÑBit 14 of the RSTRT1 general-purpose I/O port B. RSTRT1ÑSCC1 serial CAM interface outputs that marks the start of a frame. MOTOROLA Chapter 13. External Signals 13-17...
Page 344 Ethernet. PC[6] Hi-Z Bidirectional General-Purpose I/O Port C Bit 6ÑBit 6 of the general-purpose I/O port C. L1RSYNCB CD3ÑCarrier detect modem line for SCC3. L1RSYNCBÑReceive sync input for the serial interface TDMb. 13-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 345 PD[6] Hi-Z Bidirectional General-Purpose I/O Port D Bit 6ÑBit 6 of the RTS4 general-purpose I/O port D. RTS4ÑActive low request to send output indicates that SCC4 is ready to transmit data. MOTOROLA Chapter 13. External Signals 13-19...
Page 346 Available for MPC860 Rev. B and later only when PA9 or PA8 is not used as RXD4 or TXD4 functions. Available for MPC860 Rev. B and later. Pulled up on rev 0 to rev A.3 Hi-Z on rev 0 to rev A.3 13-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 347 4 Disable buffer as output 5 Pull-up resistor maintains logic high state; other driver can drive signal Note: Events 1 and 4 can be in quick succession. Figure 13-4. Three-State Buffers and Active Pull-Up Buffers MOTOROLA Chapter 13. External Signals 13-21...
Page 348 Typical values are on the order of 5 KW but can vary by approximately a factor of 2. 13.4 Recommended Basic Pin Connections The following sections provided recommended pin connections. 13-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 349 Recommendations on conÞguration of the JTAG pins (including TMS, TRST, TDI, TDO, and TCK) are made in Section 38.6, ÒRecommended TAP ConÞguration.Ó TCK/DSCK or ALE_B/DSCK/AT1 (depending on the conÞguration of the DSCK function) should be connected to ground through a pull-down resistor to disable Debug MOTOROLA Chapter 13. External Signals 13-23...
Page 350 The behavior of these signals is shown in Table 13-3. 13-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 351 DSCK/AT1: high impedance IP_B[0Ð1]/IWP[0Ð1]/VFLS[0Ð1] IP_B[0Ð1]: high impedance. IWP[0Ð1]: high VFLS[0Ð1]: low IP_B3/IWP2/VF2 IP_B3: high impedance IWP2: high VF2: low IP_B4/LWP0/VF0 IP_B4: high impedance LWP0: high VF0: low IP_B5/LWP1/VF1 IP_B5: high impedance LWP1: high; VF1: low MOTOROLA Chapter 13. External Signals 13-25...
Page 352 Part IV. Hardware Interface 13-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 353 External devices can accept or provide 8, 16, and 32 bits in parallel and must follow the handshake protocol described in this section. The maximum number of bits accepted or provided during a bus transfer is deÞned as port width. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-1...
Page 354 These signals are valid at the rising edge of the clock in which the transfer start signal (TS) is asserted. 14.3 Bus Interface Signal Descriptions Figure 14-2 shows the bus signals for the MPC860. 14-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 355 Driven high indicates that a read access is in progress. Driven low indicates that a write access is in progress. Sampled by the MPC860 when an external device initiates a transaction and the memory controller was conÞgured to handle external master accesses. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-3...
Page 356 Reservation/ cycle. See Section 14.4.9, ÒMemory Reservation.Ó Retry For regular transactions, the slave device drives this signal to indicate that the MPC860 must relinquish the bus and retry the cycle. 14-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 357 Driven by the slave device to which the current transaction was addressed. Burst Inhibit Indicates that the current slave does not support burst mode. Driven by the MPC860 when the on-chip memory controller controls the slave. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-5...
Page 358 The basic transfer protocol deÞnes the sequence of actions required for a complete MPC860 bus transaction. Figure 14-3 shows a simpliÞcation of the basic transfer protocol. Arbitration Address transfer Data transfer Termination Figure 14-3. Basic Transfer Protocol 14-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 359 Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Receives Address Returns data Asserts Transfer Acknowledge (TA) Receives data Figure 14-4. Basic Flow Diagram of a Single-Beat Read Cycle MOTOROLA Chapter 14. MPC860 External Bus Interface 14-7...
Page 360 Part IV. Hardware Interface CLKOUT Receive BG and BB negated Assert BB, drive address and assert TS A[0Ð31] TSIZ[0Ð1], AT[0Ð3] BURST Data Data is Valid Figure 14-5. Single-Beat Read CycleÐBasic TimingÐZero Wait States 14-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 361 The basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer. The following ßow and timing diagrams show the handshakes as applicable to the Þxed transaction protocol. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-9...
Page 362 Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Drives data Asserts Transfer Acknowledge (TA) Interrupts data driving Figure 14-7. Basic Flow of a Single-Beat Write Cycle 14-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 363 Part IV. Hardware Interface CLKOUT Receive BG and BB negated Assert BB, drive address and assert TS A[0Ð31] TSIZ[0Ð1], AT[0Ð3] BURST Data Data is sampled Figure 14-8. Basic Timing: Single-Beat Write Cycle, Zero Wait States MOTOROLA Chapter 14. MPC860 External Bus Interface 14-11...
Page 364 The general case of single-beat transfers assumes that external memory has a 32-bit port size. The MPC860 provides an effective mechanism for interfacing with 16- and 8-bit port size memories by allowing transfers to these devices when they are controlled by the internal memory controller. 14-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 365 TA after each word transferred on the data bus. The MPC860 also supports burst-inhibited transfers for slave devices that do not support bursting. For this type of cycle, the selected slave device MOTOROLA Chapter 14. MPC860 External Bus Interface 14-13...
Page 366 In the case of 32-bit port size, the burst includes 4 beats. When the port size is 16 bits and controlled by the internal memory controller, the burst includes 8 beats. When the port size is 8 bits and controlled by the internal memory controller, the burst includes 16 beats. The 14-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 367 0 ® data 1 ® data 2 ® data 3 ® data 0 ¥ Case burst of eight: data 0 ® data 1 ® data 2 ® ..® data 6 ® data 7 ® data 0 MOTOROLA Chapter 14. MPC860 External Bus Interface 14-15...
Page 368 Receives Data BDIP asserted Negates Burst Data in Progress (BDIP) DonÕt drive data Returns data asserts Transfer Acknowledge (TA) Receives data BDIP asserted DonÕt drive data Figure 14-11. Basic Flow of a Burst-Read Cycle 14-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 369 A[0Ð31], AT[0Ð3] TSIZ[0Ð1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Figure 14-12. Burst-Read Cycle: 32-Bit Port Size, Zero Wait State MOTOROLA Chapter 14. MPC860 External Bus Interface 14-17...
Page 370 CLKOUT A[0Ð31], AT[0Ð3] TSIZ[0Ð1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Wait State Figure 14-13. Burst-Read CycleÐ32-Bit Port SizeÐOne Wait State 14-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 371 TSIZ[0Ð1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Wait State Figure 14-14. Burst-Read CycleÐ32-Bit Port SizeÐWait States between Beats MOTOROLA Chapter 14. MPC860 External Bus Interface 14-19...
Page 372 Part IV. Hardware Interface CLKOUT A[0Ð31], AT[0Ð3] TSIZ[0Ð1] BURST BDIP Data Figure 14-15. Burst-Read Cycle: One Wait State between Beats (16-Bit Port Size) 14-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 373 Negates Burst Data in Progress (BDIP) DonÕt sample next data Asserts Transfer Acknowledge (TA) Stops driving data BDIP asserted DonÕt sample next data Figure 14-16. Basic Flow of a Burst Write Cycle MOTOROLA Chapter 14. MPC860 External Bus Interface 14-21...
Page 374 Part IV. Hardware Interface CLKOUT A[0Ð31], AT[0Ð3] TSIZ[0Ð1] BURST Last beat Will drive another data BDIP Data Data is Data is Data is Data is sampled sampled sampled sampled Figure 14-17. Burst-Write CycleÐ32-Bit Port SizeÐZero Wait States 14-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 375 ¥ Word access must have A[30Ð31] = 0b00. ¥ For burst accesses A[30Ð31] = 0b00. Misaligned accesses performed by the CPU are broken into multiple bus accesses with natural alignment. Misaligned accesses performed by external masters are not supported. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-23...
Page 376 Figure 14-20 shows the device connections on the data bus. Interface Output Register D[0Ð7] D[8Ð15] D[16Ð23] D[24Ð31] 32-Bit Port Size 16-Bit Port Size 8-Bit Port Size Figure 14-20. Interface to Different Port Size Devices 14-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 377 Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. A device needing the bus asserts BR, and then waits for the arbiter to assert BG. The new MOTOROLA Chapter 14. MPC860 External Bus Interface...
Page 378 The arbiter asserts BG to indicate that the bus is granted to the requesting device. BG can be negated after BR is negated or it can remain asserted to park the current master on the bus. When conÞgured for external central arbitration, BG is an input to the MPC860 from 14-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 379 BB, regardless of how many cycles have passed since the previous master relinquished the bus. See Figure 14-22. External Bus Master MPC860 Slave 2 Figure 14-22. Masters Signals Basic Connection MOTOROLA Chapter 14. MPC860 External Bus Interface 14-27...
Page 380 MPC860 grants the bus to the external device. Figure 14-24 shows the internal Þnite state machine that implements the arbiter protocol. 14-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 381 This situation indicates that an external pull-up resistor should be connected to TS to avoid having a slave recognize this signal as asserted when no master drives it; see Figure 14-22. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-29...
Page 382 These types are designated as either a normal/alternate master cycle, user/supervisor (problem/privilege), and instruction/data types. The address type signals are valid at the rising edge of the clock in which the special transfer start (STS) signal is asserted. 14-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 383 Core-initiated, normal instruction, program trace, user mode Core-initiated, normal instruction, user mode Core-initiated, reservation data, user mode Core-initiated, normal data, user mode DMA-initiated, normal, AT[1Ð3] user-programmable (see IDMA and DMA function code registers) MOTOROLA Chapter 14. MPC860 External Bus Interface 14-31...
Page 384 (PTR and RSV), if desired. ¥ PTR is low when the following is true: Ñ AT0 = 0 (CPU access) Ñ AT2 = 0 (Instruction) Ñ AT3 = 0 (Program Trace) 14-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 385 See Figure 14-25 and Figure 14-26. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-33...
Page 386 The protocol tries to optimize reservation cancellation such that a PowerPC processor is notiÞed of memory reservation loss on a remote bus only when it has issued a STWCX cycle to that address. 14-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 387 ¥ Holds one reservation for each local master capable of memory reservations. ¥ Sets the reservation when that master issues a load and reserve request. ¥ Clears the reservation when another master issues a store to the reservation address. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-35...
Page 388 The advantage of KR is that it is cheaper and easier to implement. Figure 14-28 shows the reservation protocol for a multi-level (local) bus. The system describes a situation in which the reserved location is in the remote bus. 14-36 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 389 To properly control termination of a bus cycle for a bus error, TEA must be asserted at the same time or before TA is asserted. TEA should be negated MOTOROLA Chapter 14. MPC860 External Bus Interface...
Page 390 BR and BB are negated together. Normal arbitration resumes one clock cycle later. CLKOUT BG (Output) Allow external master to gain the bus A[0Ð31] TSIZ[0Ð1] BURST Data RETRY Figure 14-29. Retry Transfer TimingÐInternal Arbiter 14-38 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 391 When RETRY is asserted as a termination signal on the second or third data beat of the access (being the Þrst data beat acknowledged by a normal TA assertion), it is processed by the MPC860 as a TEA. MOTOROLA Chapter 14. MPC860 External Bus Interface 14-39...
Page 392 MPC860 to complete the access process the RETRY assertion as a TEA. Table 14-6 summarizes how the MPC860 recognizes the termination signals provided by the slave device that is addressed by the initiated transfer. 14-40 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 393 Part IV. Hardware Interface Table 14-6. Termination Signals Protocol RETRY/KR Action Asserted Transfer error termination Negated Asserted Normal transfer termination Negated Negated Asserted Retry transfer termination/kill reservation MOTOROLA Chapter 14. MPC860 External Bus Interface 14-41...
Page 394 Part IV. Hardware Interface 14-42 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 395 ¥ Clock dividers are provided for low-power modes and internal clocks ¥ Contains Þve major power-saving modes Ñ Normal (high and low) Ñ Doze (high and low) Ñ Sleep Ñ Deep sleep Ñ Power down MOTOROLA Chapter 15. Clocks and Power Control 15-1...
Page 396 (¸4 or ¸16) dividers Clock brgclk Drivers syncclk CLKOUT CLKOUT Driver tmbclk tbclk TMBclk Driver rtdiv rtsel ¸4 RTC /PIT Clock pitrtclk and DRIVER XTAL CRYSTAL EXTAL ¸512 Oscillator (OSCM) Figure 15-1. Clock Source and Distribution 15-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 397 EXTCLK. This is because noise from the EXTCLK clock source will couple into the crystal oscillator circuit, and will in many cases not allow the system phase-locked loop (SPLL) to lock. The converse, however, is allowable; EXTCLK MOTOROLA Chapter 15. Clocks and Power Control 15-3...
Page 398 Motorola reserves the right to perform these changes, and designers should be prepared to modify their crystal circuits appropriately should these changes cause their crystal circuit 15-4 MPC860 PowerQUICC UserÕs Manual...
Page 399 Second, the programmability of the oscillator enables the system to operate at a variety of frequencies with only a single external clock source. The MPC860 SPLL block diagram is shown in Figure 15-4. MOTOROLA Chapter 15. Clocks and Power Control 15-5...
Page 400 MODCK[1-2] pins. The SPLL immediately begins to use the multiplication factor PLPRCR[MF] value and external clock source for OSCCLK determined by the sampled MODCK[1-2] pin and attempts to achieve lock; therefore, the MODCK[1-2] signals should 15-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 401 For input frequencies greater than 15 MHz and (MF+1)£2, this jitter is less than ±0.6ns. Otherwise, this jitter is not guaranteed. However, for (MF+1)<10 and input frequencies greater than 10 MHz, this jitter is less than ±2ns. MOTOROLA Chapter 15. Clocks and Power Control 15-7...
Page 402 If there is no overlap between two ranges of operation, choose the minimum or maximum value of the recommended XFC range for the normal operating frequency of the system, whichever is nearest the range for the other frequency. 15-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 403 The MPC860 uses the following 9 internal clock signals, which are derived from the SPLL output clock (VCOOUT): ¥ General system clocksÑGCLK1C, GCLK2C, GCLK1, GCLK2 ¥ Memory controller and external bus clocksÑGCLK1_50, GCLK2_50 ¥ Baud rate generator clockÑBRGCLK ¥ Synchronization clocksÑSYNCCLK, SYNCCLKS MOTOROLA Chapter 15. Clocks and Power Control 15-9...
Page 404 CPM. They are not active when the MPC860 is in sleep or deep-sleep modes. GCLKx can be dynamically switched between two different frequencies determined by dividers programmed in SCCR[DFNH] and SCCR[DFNL], as shown in Figure 15-6. 15-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 405 The external bus clocks GCLK1_50 and GCLK2_50 are derived from GCLK1 and GCLK2, as determined by the SCCR[EBDF]. SCCR[EBDF] is cleared by HRESET, and thus GCLK1_50 and GCLK2_50 default to GCLK1 and GCLK2. The MOTOROLA Chapter 15. Clocks and Power Control 15-11...
Page 406 The low-power frequency dividers described in Section 15.3.1.1, ÒThe Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2)Ó also effect the frequency and duty cycle of GCLK1_50, GCLK2_50, and CLKOUT. For an example of this, see Figure 15-9. 15-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 407 CLKOUT reduces power consumption, noise, and electromagnetic interference on the printed circuit board. While the SPLL is acquiring lock, the CLKOUT signal does not oscillate and remains in a low state. MOTOROLA Chapter 15. Clocks and Power Control 15-13...
Page 408 SYNCCLK) are used by the signal synchronization circuitry in the serial ports of the communication processor module. The signal synchronization circuitry is used to sample and synchronize asynchronous external signals provided to these ports. SYNCCLK allows 15-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 409 32.768 KHz or 38.4 KHz crystal with the OSCM be used for the PITRTCLK source if the RTC is to be used. MOTOROLA Chapter 15. Clocks and Power Control 15-15...
Page 410 The various modules of the MPC860 are connected to four distinct power rails. These power rails have different requirements, as explained in the following sections. The organization of the power rails is shown in Figure 15-12. 15-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 411 RTC, PIT, TB, and DEC 15.4.1 I/O Buffer Power (VDDH) The I/O buffers, logic, and clock control are fed by a 3.3V power supply. VDDH must in all cases be greater than or equal to VDDL. MOTOROLA Chapter 15. Clocks and Power Control 15-17...
Page 412 When the CPM is idle, it uses its own power-saving mechanism to shut down automatically. Low-power modes are controlled in the PLPRCR[LPM] and PLPRCR[CSRC]. Events can cause automatic changes from one low-power mode to another. These events include 15-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 413 32 KHz ~10mA, LPM=11 from RTC, + power supply KAPWR = 3.0V TEXPS=0 PIT, DEC, wake-up Temperature = 50° C TB followed (PwSp_Wake+ 16 by external ms at 32 KHz) hard reset MOTOROLA Chapter 15. Clocks and Power Control 15-19...
Page 414 Software is active only in normal high/low modes. Software initiation of power-down mode requires that the TEXP output be used by external logic to gate main power (VDDH, VDDL, and VDDSYN). MPC860 Figure 15-13. Low-Power Mode Flowchart 15-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 415 GCLKxC clocks to the core, MMUs, and caches are disabled. However, the CPM and SIU continue to function as normal. Doze high mode selected PLPRCR[CSRC]=0, MSR[POW]=1, PLPRCR[LPM]=01. In doze high mode, the GCLKx frequency is determined by MOTOROLA Chapter 15. Clocks and Power Control 15-21...
Page 416 SCCR[PRQEN] is set; otherwise it will enter normal low mode. Upon resumption of processing in normal high or low mode, the MPC860 will jump to the external interrupt vector to process the interrupt source. When the core returns from the 15-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 417 500 OSCCLK clocks (if OSCCLK is sourced by OSCM) or a maximum of 1000 clocks (if OSCCLK is sourced by EXTCLK). Deep-sleep mode is selected if PLPRCR[LPM]=11 and PLPRCR[TEXPS]=1. Note also that PLPRCR[TMIST] should be cleared before entering deep-sleep mode; for more MOTOROLA Chapter 15. Clocks and Power Control 15-23...
Page 418 Figure 15-14. The MPC860 should then go through a normal hardware reset sequence. When performing this hardware reset sequence, it is important to allow enough time for the oscillator to warm up and the SPLL to lock. 15-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 419 (RTC) if a power shutdown or power failure should occur. The backup KAPWR source is used to maintain the RTC. In this conÞguration, no provision is made for automatic wake-up from power-down mode. Instead, it is assumed that the appropriate reset MOTOROLA Chapter 15. Clocks and Power Control 15-25...
Page 420 (when software clears PLPRCR[TMIST]). Note, however, this requires that PLPRCR[TMIST] must be cleared before entry into any low-power mode other than normal high mode. 15-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 421 The COM Þeld is cleared by hard reset. 00 =Clock output enabled full-strength buffer. 01 =Clock output enabled half-strength output buffer. 10 =Reserved. 11 =Clock output disabled. 3Ð5 Ñ Reserved, should be cleared. MOTOROLA Chapter 15. Clocks and Power Control 15-27...
Page 422 BRGCLK signal. Changing the value of this Þeld does not result in a loss-of-lock condition. This Þeld is cleared by a power-on or hard reset. 00 = Divide by 1 (normal operation). 01 = Divide by 4. 10 = Divide by 16. 11 = Divide by 64. 15-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 423 15.6.2 PLL, Low-Power, and Reset Control Register (PLPRCR) The 32-bit system PLL, low-power, and reset control register (PLPRCR) is powered by a keep-alive power supply and is used to control the system frequency and low-power mode operation. MOTOROLA Chapter 15. Clocks and Power Control 15-29...
Page 424 When TEXPS is set, the TEXP external signal is asserted and when it is reset, the TEXP external signal is negated. 0 = TEXP is negated. 1 = TEXP is asserted. Ñ Reserved, should be cleared. 15-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 425 Table 15-10 describes PLPRCR[CSR] and DER[CHSTPE] bit combinations. Table 15-10. PLPRCR[CSR] and DER[CHSTPE] Bit Combinations PLPRCR[CSR] DER[CHSTPE] Checkstop Mode Result Ñ Ñ Ñ Enter debug mode Ñ Automatic reset Ñ Enter debug mode MOTOROLA Chapter 15. Clocks and Power Control 15-31...
Page 426 Part IV. Hardware Interface 15-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 427 The following is a list of the memory controllerÕs main features: ¥ Eight memory banks Ñ 32-bit address decode with mask Ñ Variable block sizes (32 Kbytes to 4 Gbytes) Ñ Byte parity generation/checking MOTOROLA Chapter 16. Memory Controller 16-1...
Page 428 Ñ Internal address multiplexing for all on-chip bus masters supporting 64-, 128-, 256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, 256-Mbyte page banks Ñ Glueless interface to EDO, self refresh, and synchronous DRAM devices 16-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 429 Memory Command Register (MCR) Memory Data Register (MDR) Parity Error Memory Status Register (MSTAT) DP[0Ð3] Memory Address Register (MAR) Parity DP[0Ð31] Logic Memory Periodic Timer Prescale Register (MPTPR) Figure 16-1. Memory Controller Block Diagram MOTOROLA Chapter 16. Memory Controller 16-3...
Page 430 (DP[0Ð3]), one for each data byte lane on the MPC860 system bus. The parity on the bus is checked only if the memory bank accessed in the current transaction has parity enabled. Parity checking/generation can be enabled for a 16-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 431 The UPM speciÞes a set of signal patterns for a user-speciÞed number of clock cycles. The UPM RAM pattern run by the memory controller is selected according to the type of external access transacted. At every clock cycle, the logical value of the external MOTOROLA Chapter 16. Memory Controller 16-5...
Page 432 Ö Memory command register (MCR) Ö Machine A mode register (MAMR) Ö Machine B mode register (MBMR) Ö Memory data register (MDR) Ö Memory address register (MAR) Ö Memory periodic timer prescaler register (MPTPR) 16-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 433 Table 16-2. Access Granularities for Predefined Port Sizes Bytes Half Words PredeÞned Words (on Word Port Size Boundaries) Even Even Ö Ö 8-bit Ñ Ñ Ñ Ö Ö Ö (on D[0Ð15]) 16-bit Ñ Ñ Ö Ö Ö Ö Ö 32-bit MOTOROLA Chapter 16. Memory Controller 16-7...
Page 434 The base registers (BR0ÐBR7) contain the base address and address types that the memory controller uses to compare the value on the address bus with the current address accessed. It also includes a memory attribute and selects the machine for memory operation handling. 16-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 435 Addr (IMMR & FFFF0000) + 0x100 Field PARE Ñ Reset 00_000 Addr (IMMR & FFFF0000) + 0x102 This value depends on the value of the hard reset conÞguration word. Figure 16-6. BR0 Reset Defaults MOTOROLA Chapter 16. Memory Controller 16-9...
Page 436 1 This bank is valid. The CS signal does not assert until V is set. 16.4.2 Option Registers (ORx) The option registers (OR0ÐOR7), shown in Figure 16-7, contain the address and address type mask bit for address bus comparison. It also includes all GPCM parameters. 16-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 437 17 18 19 24 25 26 27 Field CSNT/SAM ACS/G5LA,G5LS BIH SETA TRLX EHTR Ñ Reset 1111 OR0: R; R/W for all others Addr (IMMR & FFFF0000) + 0x106 Figure 16-8. OR0 Reset Defaults MOTOROLA Chapter 16. Memory Controller 16-11...
Page 438 0 Internal or external transfer acknowledge can acknowledge this access, whichever comes Þrst. 1 The memory controller does not generate TA for this bank; instead the peripheral must generate it on the external TA signal. 16-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 439 Ñ Reserved, should be cleared. 16.4.4 Machine A Mode Register/ achine B Mode Registers (MxMR) The machine x mode register (MAMR and MBMR) contain the conÞguration for UPMA and UPMB, respectively. See Figure 16-1. MOTOROLA Chapter 16. Memory Controller 16-13...
Page 440 The maximum disable period is four clock cycles. If more than 4 cycles are required, they must be added explicitly in the UPM RAM words. 00 1-cycle disable period 01 2-cycle disable period 10 3-cycle disable period 11 4-cycle disable period Ñ Reserved, should be cleared. 16-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 441 UPM pattern to initialize SDRAM. Field Ñ Ñ Reset 0000_0000_0000_0000 Addr (IMMR & FFFF0000) + 0x168 Field Ñ MCLF Ñ Reset 0000_0000_0000_0000 Addr (IMMR & FFFF0000) + 0x16A Figure 16-11. Memory Command Register (MCR) MOTOROLA Chapter 16. Memory Controller 16-15...
Page 442 MDR must be set up before issuing a write command to READ WRITE the MCR. Field Reset 0000_0000_0000_0000 Address (IMMR & FFFF0000) + 0x17C Field Reset 0000_0000_0000_0000 Address (IMMR & FFFF0000) + 0x17E Figure 16-12. Memory Data Register (MDR) 16-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 443 See Section 15.3, ÒClock Signals.Ó Field Ñ Reset 0000_001x 0000_0000 Addr (IMMR & FFFF0000) + 0x17A Figure 16-14. Memory Periodic Timer Prescaler Register (MPTPR) MOTOROLA Chapter 16. Memory Controller 16-17...
Page 444 If BRx[MS] selects the GPCM, the attributes for the memory cycle are taken from ORx. These attributes include the CSNT, ACS[0Ð1], SCY[0Ð3], TRLX, EHTR, and SETA Þelds. See Table 16-11 for signal behavior and system response. 16-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 445 Figure 16-16 shows a basic connection between the MPC860 and an external peripheral device. Here, CS (the strobe output for the memory access) is connected directly to CE of the memory device and R/W is connected to the respective R/W in the peripheral device. 16-19 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 446 Here, CS is connected directly to CE of the memory device. The WE signals are connected to the respective W signal in the memory device where each WE corresponds to a different data byte. 16-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 447 Figure 16-20. Clock Address CSNT = 1 Data Figure 16-19. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0) MOTOROLA Chapter 16. Memory Controller 16-21...
Page 448 MPC860 memory controller. See Figure 16-21 and Figure 16-22. Clock Address ACS = 10 ACS = 11 Data Figure 16-21. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, and TRLX = 1) 16-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 449 (SETA and TRLX = 1), the memory controller does not support external devices that provide TA to complete the transfer with zero wait states. The minimum access duration in this case is 3 clock cycles. MOTOROLA Chapter 16. Memory Controller 16-23...
Page 450 Figure 16-23 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1, TRLX =1) Clock Address Data Figure 16-24. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX =1) 16-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 451 See Figure 16-25 through Figure 16-28 for details. Clock Address Data Hold Time Figure 16-25. GPCM Read Followed by Write (EHTR = 0) MOTOROLA Chapter 16. Memory Controller 16-25...
Page 452 Long hold time allowed Figure 16-26. GPCM Write Followed by Read (EHTR = 1) Clock Address Data Hold Time Long hold time allowed Figure 16-27. GPCM Read Followed by Read from Different Banks (EHTR = 1) 16-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 453 BR0. After the Þrst write to OR0, the boot chip-select can only be restarted on hardware reset. The initial values of the boot bank in the memory controller are described in Table 16-12. MOTOROLA Chapter 16. Memory Controller 16-27...
Page 454 Figure 16-30 shows the timing for TRLX = 0 when an external asynchronous master accesses SRAM. TA, WE, and OE remain asserted until the external master negates AS, at which point they deassert asynchronously. 16-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 455 During a burst cycle, the user sees the chip-select assertion follow the same pattern as for a single-beat cycle. However, BI remains negated, and the burst continues for the following data beats after the negation of chip-select following TA for the Þrst data beat. MOTOROLA Chapter 16. Memory Controller 16-29...
Page 456 RAM word from the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. If the UPM reads a RAM word with WAEN set, the external UPWAIT signal is sampled and synchronized by the memory controller and the current request is frozen. 16-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 457 BRx. The value in BRx[MS] selects the UPM to handle the memory access. The user must ensure that the UPM is appropriately initialized before a request. MOTOROLA Chapter 16. Memory Controller 16-31...
Page 458 TEA, SRESET, or HRESET. The UPM provides a mechanism by which memory control signals can meet the timing requirements of the device without losing data. The mechanism is the exception pattern which deÞnes how the UPM deasserts its signals in a controlled manner. 16-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 459 In Figure 16-35, if SCCR[EBDF] = 01, CLKOUT equals the system clock divided by 2. In this scheme GCLK1_50 does not have a 50% duty cycle. System Clock CLKOUT GCLK1_50 GCLK2_50 Clock Phase Figure 16-35. UPM Clock Scheme Two (Division Factor = 2) MOTOROLA Chapter 16. Memory Controller 16-33...
Page 460 GPL1 G1T4 G1T3 G1T4 G1T4 G1T3 GPL2 G2T4 G2T3 G2T4 G1T4 G2T3 Clock Phase RAM Word 1 RAM Word 2 Figure 16-36. UPM Signals Timing Example One (Division Factor = 1, EBDF = 00) 16-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 461 RAM Array Words Deep GCLK2_50 Signals Timing Generator CS Signal BS Signal Selected Bank TSIZ, PS, A[30Ð31] Selector Selector CS[0Ð7] GPL0 GPL1 GPL2 GPL3 GPL4 GPL5 BS[0Ð3] Figure 16-38. RAM Array and Signal Generation MOTOROLA Chapter 16. Memory Controller 16-35...
Page 462 1 Negated at the rising edge of GCLK1_50. The Þnal value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30Ð31] for the access. See Section 16.6.4.3, ÒByte-Select Signals (BxTx).Ó 16-36 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 463 0 The data bus should be sampled at the rising edge of GCLK2_50 for a read in this cycle. 1 The data bus should be sampled at the falling edge of GCLK2_50 for a read in this cycle. MOTOROLA Chapter 16. Memory Controller...
Page 464 TA is output at the rising edge of GCLK2_50. 0 TA is driven low on the rising edge of GCLK2_50. The bus master samples it low in the next clock cycle. 1 TA is driven high on the rising edge of GCLK2_50. 16-38 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 465 BSTx bit and the values of BRx[PS], TSIZn, and A[30Ð31] in the current cycle.The BS signals are also controlled by the port size of the accessed bank, the transfer size of the transaction, and the address accessed. Figure 16-41 shows how UPMs control BS signals. MOTOROLA Chapter 16. Memory Controller 16-39...
Page 466 G5LS, as shown in Figure 16-42. This allows it to assert earlier (simultaneous with TS, for an internal master), which can speed up the memory interface, particularly when GPL5 is used as a control signal for external address multiplexers. 16-40 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 467 UPM cycle. GPL_A5 is driven low at the falling edge of GCLK1_50 in the current UPM cycle. GPL_A5 is driven high at the falling edge of GCLK1_50 in the current UPM cycle. MOTOROLA Chapter 16. Memory Controller 16-41...
Page 468 Continued loop execution depends on the loop counter. If the counter is not zero, the next RAM word executed is the loop start word. Otherwise, the next RAM word executed is the one after the loop end word. Loops can be executed sequentially but cannot be nested. 16-42 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 469 RAM word, as shown in Figure 16-43. The AMX Þeld can be used to output the contents of MAR on the address signals. Figure 16-43 shows address multiplex timing. MOTOROLA Chapter 16. Memory Controller 16-43...
Page 470 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Address Multiplexing A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 is Enabled Ñ A10 A11 A12 A13 A14 A15 A16 A17 A18 16-44 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 471 A20ÐA31 16 Mbyte A19ÐA31 32 Mbyte A18ÐA31 64 Mbyte A17ÐA31 16 Mbyte A20ÐA31 32 Mbyte A19ÐA31 64 Mbyte A18ÐA31 128 Mbyte A17ÐA31 256 Mbyte A16ÐA31 64 Mbyte A19ÐA31 128 Mbyte A18ÐA31 256 Mbyte A17ÐA31 MOTOROLA Chapter 16. Memory Controller 16-45...
Page 472 A17ÐA30 64 Mbyte A16ÐA30 8 Mbyte A20ÐA30 16 Mbyte A19ÐA30 32 Mbyte A18ÐA30 64 Mbyte A17ÐA30 32 Mbyte A19ÐA30 64 Mbyte A18ÐA30 128 Mbyte A17ÐA30 256 Mbyte A16ÐA30 128 Mbyte A18ÐA30 256 Mbyte A17ÐA30 16-46 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 473 1/2 clock early, which can be useful during burst reads. This feature should be used only in systems without external synchronous bus devices. MOTOROLA Chapter 16. Memory Controller 16-47...
Page 474 If the WAEN bit is set and UPWAIT was sampled high on the previous falling edge of GCLK2_50, the logical value of the external signals are frozen to the value deÞned at the 16-48 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 475 AS should deassert (similar to DTACK in the 68000 bus). The wait state is exited when AS is negated, at which point all external signals controlled by the UPM are driven high asynchronously from the AS deassertion. External signals are MOTOROLA Chapter 16. Memory Controller 16-49...
Page 476 MAMR[GPLA4DIS] and MBMR[GPLB4DIS] enable this mechanism. ¥ The external TA mechanism is used only in accesses controlled by the GPCM. ORx[SETA] speciÞes whether TA is generated internally or externally. The following examples show how the two mechanisms work. 16-50 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 477 Synchronous masters initiate a transfer by asserting TS. A[0Ð31], RD/WR, BURST, and TSIZ must be stable before the rising edge of CLKOUT after TS is asserted and until the last TA is negated. Because the external master operates synchronously with the MPC860, MOTOROLA Chapter 16. Memory Controller 16-51...
Page 478 A wait mechanism in the UPM supports handshaking for external asynchronous masters. This is provided with an AS input signal and the WAEN bit in the UPM RAM words. See Section 16.6.4.11, ÒThe Wait Mechanism (WAEN).Ó 16-52 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 479 Asynchronous external masters behave as described in Section 16.5.3, ÒExternal Asynchronous Master Support.Ó CLKOUT A[6Ð27] A[28Ð31] BURST TSIZ Data Address Memory Match and Device Compare Access Figure 16-47. Synchronous External Master Access MOTOROLA Chapter 16. Memory Controller 16-53...
Page 480 ORx[G5LS]. In this example, the accessed critical word is addressed at BADDR[28Ð29] = 10, which then increments and wraps around to the word before the critical word (01) for subsequent beats of this burst access. 16-54 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 481 Part IV. Hardware Interface DRAM BS[0Ð3] Bank GPL_A5 Multiplexer BADDR[28Ð30] A[6Ð31] D[0Ð31] BURST External MPC860 Master TSIZ[0Ð1] Figure 16-49. Synchronous External Master Interconnect Example MOTOROLA Chapter 16. Memory Controller 16-55...
Page 482 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 16-50. Synchronous External Master: Burst Read Access to Page Mode DRAM 16-56 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 483 The state of GPL_A5 in the Þrst clock cycle of the memory device access is determined by the value of the corresponding ORx[G5LS]. DRAM BS[0Ð3] GPL_A5 Multiplexer A[6Ð31] D[0Ð31] External Master TSIZ[0Ð1] MPC860 Arbitration Signals External Arbiter Figure 16-51. Asynchronous External Master Interconnect Example MOTOROLA Chapter 16. Memory Controller 16-57...
Page 484 16.9 Memory System Interface Examples The following examples show how to connect and set up the UPM RAM array for two types of DRAMÑpage mode DRAM and page mode extended data-out DRAM. The values used 16-58 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 485 RAM array. A blank cell in the Þgures indicates a donÕt care bit, which is typically programmed to logic 1 to conserve power. MOTOROLA Chapter 16. Memory Controller 16-59...
Page 486 Selects two disable timer clock cycles GPLA4DIS Disables the UPWAITA signal RLFA 0011 Selects three loop iterations for read WLFA 0011 Selects three loop iterations for write Selects column address on Þrst cycle Supports burst accesses 16-60 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 487 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 Figure 16-54. Single-Beat Read Access to Page-Mode DRAM MOTOROLA Chapter 16. Memory Controller 16-61...
Page 488 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS WSS+1 WSS+2 Figure 16-55. Single-Beat Write Access to Page Mode DRAM 16-62 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 489 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 16-56. Burst Read Access to Page-Mode DRAM (No LOOP) MOTOROLA Chapter 16. Memory Controller 16-63...
Page 490 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 Figure 16-57. Burst Read Access to Page-Mode DRAM (LOOP) 16-64 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 491 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 Figure 16-58. Burst Write Access to Page-Mode DRAM (No LOOP) MOTOROLA Chapter 16. Memory Controller 16-65...
Page 492 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS WBS+1 WBS+2 WBS+3 WBS+4 Figure 16-59. Burst Write Access to Page-Mode DRAM (LOOP) 16-66 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 493 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 Figure 16-60. Refresh Cycle (CAS before RAS) to Page-Mode DRAM MOTOROLA Chapter 16. Memory Controller 16-67...
Page 494 DRAM access time. For a 16-bit port size memory, the reduction is from 17 to 10 cycles and when an 8-bit port size memory is connected, the reduction is from 33 to 18 cycles. 16-68 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 495 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 Figure 16-62. Optimized DRAM Burst Read Access MOTOROLA Chapter 16. Memory Controller 16-69...
Page 496 Þgures show the RAM array contents that handle each of the possible cycles; each column represents a different word in the RAM array. A blank cell indicates a donÕt care bit (typically programmed to logic 1 to conserve power). 16-70 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 497 Selects two disable timer clock cycles GPLB4DIS MBMR Disables the UPWAITB signal RLFB MBMR 0011 Selects three loop iterations for read WLFB MBMR 0011 Selects three loop iterations for write Selects column address on Þrst cycle Supports burst accesses MOTOROLA Chapter 16. Memory Controller 16-71...
Page 498 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 RSS+3 RSS+4 Figure 16-64. EDO DRAM Single-Beat Read Access 16-72 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 499 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS WSS+1 WSS+2 WSS+3 Figure 16-65. EDO DRAM Single-Beat Write Access MOTOROLA Chapter 16. Memory Controller 16-73...
Page 500 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 RBS+9 RBS+10 Figure 16-66. EDO DRAM Burst Read Access 16-74 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 501 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS WBS+1 WBS+2 WBS+3 WBS+4 WBS+5 WBS+6 WBS+7 WBS+8 WBS+9 Figure 16-67. EDO DRAM Burst Write Access MOTOROLA Chapter 16. Memory Controller 16-75...
Page 502 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 PTS+3 PTS+4 Figure 16-68. EDO DRAM Refresh Cycle (CAS before RAS) 16-76 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 503 Ð Bit 22 Ð Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 Figure 16-69. EDO DRAM Exception Cycle MOTOROLA Chapter 16. Memory Controller 16-77...
Page 504 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 xxS+1 xxS+2 xxS+3 xxS+4 xxS+5 xxS+6 xxS+7 xxS+8 xxS+9 xxS+10 Figure 16-70. Blank Work Sheet for a UPM 16-78 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 505 Signals shared among all sockets consist of the address and data buses, socket control signals, and synchronous socket status signals. A[6Ð31] and D[0Ð15] are the address and data signals of the system bus. Figure 17-1 shows the PCMCIA host adapter moduleÕs external signals. MOTOROLA Chapter 17. PCMCIA Interface 17-1...
Page 506 (IORD),(IOWR) (IORD_A),(IOWR_A) RESET_A/B buffer with OE POE_A/B Transparent latch with OE Address_A[25:0] A[6:31] REG_A ALE_A/B Vcc_A WAIT_A/B, IOIS16_A/B RDY/BSY_x, BVD1_x,BVD2_x Chip Vdd CD1_x, CD2_x, VS1_x, VS2_x SPKROUT Figure 17-1. System with Two PCMCIA Sockets 17-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 507 Write enable/program. Output. During PCMCIA accesses, WE_x is used to latch memory write data to the PC card in a PCMCIA socket. Can also be used as the programming strobe for PC cards using programmable memory technologies. MOTOROLA Chapter 17. PCMCIA Interface 17-3...
Page 508 STSCHG and is generated by I/O PC cards. STSCHG must be held negated when the Òsignal on changeÓ bit and ÒchangedÓ bit in the card status register on the PC card are either or both zero. STSCHG must be asserted when both bits = 1. 17-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 509 SPKROUT Speaker out. Output. Provides a digital audio wave form to be driven to the systemÕs speaker. It is generated asa logic exclusive OR of the SPKRA and SPKRB input signals. 17.3 Operation Description This section describes the operation of memory and I/O cards, interrupt detection and handling, power control, and reset. MOTOROLA Chapter 17. PCMCIA Interface 17-5...
Page 510 (PER) to generate a PCMCIA interface interrupt. The interrupt level is user programmable and the PCMCIA interface can generate an additional interrupt for RDY/IRQ that can trigger on level (low or high) or edge (fall or rise) of the input signal. 17-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 511 PC15/14 as DREQ0/DREQ1. If the request is enabled, port C should not be programmed to be DREQ0/DREQ1. IOIS16 SPKR DREQ0 CxDREQ0 Port C CxDREQ0 Multiplexer Logic PortCDREQ0 Internal DMA Request Figure 17-2. Internal DMA Request Logic MOTOROLA Chapter 17. PCMCIA Interface 17-7...
Page 512 CAVS2 Voltage sense 2 for card A CAWP Write protect for card A CACD2 Card detect 2 for card A CACD1 Card detect 1 for card A CABVD2 Battery voltage/SPKR IN for card A 17-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 513 Voltage sense 1 for card A changed CAVS2_C Voltage sense 2 for card A changed CAWP_C Write protect for card A changed CACD2_C Card detect 2 for card A changed CACD1_C Card detect 1 for card A changed MOTOROLA Chapter 17. PCMCIA Interface 17-9...
Page 514 ECD1 CB EBVD2 CB EBVD1 Ñ CB ERDY L CB ERDY H CB ERDY R CB ERDY F Ñ Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x0FA Figure 17-5. PCMCIA Interface Enable Register (PER) 17-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 515 CB_ERDY_H Enable for RDY/IRQ card B pin is high CB_ERDY_R Enable for RDY/IRQ card B pin rising edge detected CB_ERDY_F Enable for RDY/IRQ card B pin falling edge detected 28Ð31 Ñ Reserved, should be 0. MOTOROLA Chapter 17. PCMCIA Interface 17-11...
Page 516 Card x reset. CARESET is reßected on OP0 used to reset card A. CBRESET is reßected on OP3 used to reset card B. 26Ð31 Ñ Reserved, should be cleared. 17.4.5 PCMCIA Base Registers 0Ð7 (PBR0ÐPBR7) Setting a bit in the PBR, shown in Figure 17-5, enables the corresponding interrupt. 17-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 517 0x0AC (POR5); 0x0B4 (POR6); 0x0BC (POR7) Field PSST PSLOT Reset UndeÞned Addr (IMMR & 0xFFFF0000) + 0x086 (POR0); 0x08E (POR1); 0x096 (POR2); 0x09E (POR3); 0x0A6 (POR4); 0x0AE (POR5); 0x0B6 (POR6); 0x0BE (POR7) Figure 17-8. PCMCIA Option Register 0Ð7 (POR0ÐPOR7) MOTOROLA Chapter 17. PCMCIA Interface 17-13...
Page 518 Used to meet address/data hold time requirements for slow memories and peripherals. 0000 Strobe negation to address change 0 clock 0001 Strobe negation to address change 1 clock 1111 Strobe negation to address change 15 clock 17-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 519 1 Write protected. Attempting to write to this window causes a machine check interrupt. PCMCIA valid. Indicates whether the contents of the OBR and POR pair are valid. 0This bank is invalid. 1This bank is valid. MOTOROLA Chapter 17. PCMCIA Interface 17-15...
Page 520 Part IV. Hardware Interface 17.5 PCMCIA Controller Timing Examples CLKOUT A[0Ð31] RD/WR BURST CE1-2 PCOE WAIT DATA PSST PSHT Figure 17-9 PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 1 17-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 521 Part IV. Hardware Interface CLKOUT A[0Ð31] RD/WR BURST CE1-2 PCOE WAIT DATA PSST PSHT Figure 17-10. PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 2 PSL = 4 PSHT = 1 MOTOROLA Chapter 17. PCMCIA Interface 17-17...
Page 522 Part IV. Hardware Interface CLKOUT A[0Ð31] RD/WR BURST CE1-2 PCOE WAIT DATA PSHT PSST Figure 17-11. PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 0 17-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 523 Part IV. Hardware Interface CLKOUT A[0Ð31] RD/WR BURST CE1-2 PCWE WAIT DATA PSST PSHT Figure 17-12. PCMCIA Single-Beat Write Cycle PRS = 2 PSST = 1 PSL = 3 PSHT = 1 MOTOROLA Chapter 17. PCMCIA Interface 17-19...
Page 524 Part IV. Hardware Interface CLKOUT A[0Ð31] RD/WR BURST CE1-2 IOWR WAIT DATA IO16 PSHT PSST Figure 17-13. PCMCIA Single-Beat Write Cycle PRS = 3 PSST = 1 PSL = 4 PSHT = 3 17-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 525 Part IV. Hardware Interface CLKOUT A[0Ð31] RD/WR BURST CE1-2 IOWR WAIT DATA PSHT PSST WAIT DELAY Figure 17-14. PCMCIA Single-Beat Write with Wait PRS = 3 PSST = 1 PSL = 3 PSHT = 0 MOTOROLA Chapter 17. PCMCIA Interface 17-21...
Page 526 Part IV. Hardware Interface CLKOUT A[0Ð31] RD/WR BURST CE1-2 IORD WAIT DATA PSST WAIT DELAY PSHT Figure 17-15. PCMCIA Single-Beat Read with Wait PRS = 3 PSST = 1 PSL = 3 PSHT =1 17-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 527 Part IV. Hardware Interface CLKOUT A[0Ð31] RD/WR BURST IOWR DATA IO16 PSHT PSST Figure 17-16 PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 MOTOROLA Chapter 17. PCMCIA Interface 17-23...
Page 528 Part IV. Hardware Interface CLKOUT A[0Ð31] RD/WR BURST IOWR DATA IO16 PSHT PSHT PSST PSST Figure 17-17. PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 17-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 529 A[0Ð31] AT=0XF AT=0XF RD/WR BURST CE1-2 IORD PCOE SIZE SIZE=WORD SIZE=HALF DATA PSHT PSHT PSST PSST Figure 17-18. PCMCIA DMA Read Cycle PRS = 4 PSST = 1 PSL = 3 PSHT = 0 MOTOROLA Chapter 17. PCMCIA Interface 17-25...
Page 530 Part IV. Hardware Interface 17-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 531 DMA (SDMA) channels on the MPC860 with which the CP implements sixteen virtual SDMA channels. ¥ Chapter 21, ÒSerial Interface,Ó describes the serial interface (SI) in which the physical interface to all SCCs and SMCs is implemented. MOTOROLA Part V. The Communications Processor Module...
Page 532 18-bit port B parallel I/O and allows data to be sent to and from the MPC860 over 8 or 16 parallel data lines with two handshake control signals. V-ii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 533 60x family of PowerPC microprocessors. ¥ PowerPC Microprocessor Family: The ProgrammerÕs Reference Guide (Motorola order #: MPCPRG/D) is a concise reference that includes the register summary, memory control model, exception vectors, and the PowerPC instruction set.
Page 534 (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. Table x. Acronyms and Abbreviated Terms Term Meaning Arithmetic logic unit Asynchronous transfer mode Buffer descriptor BIST Built-in self test V-iv MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 535 Integrated services digital network JTAG Joint Test Action Group LIFO Last-in-Þrst-out Least recently used Least-signiÞcant byte Least-signiÞcant bit Multiply accumulate Most-signiÞcant byte Most-signiÞcant bit Machine state register Not a number NMSI Nonmultiplexed serial interface MOTOROLA Part V. The Communications Processor Module...
Page 536 Systems network architecture Serial peripheral interface SRAM Static random access memory Time-division multiplexed Terminal endpoint of an ISDN connection Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter V-vi MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 537 The MPC860 CPM is similar to the one in the MPC850 and both are derived from the CPM in the MC68360 QUICC; see the MC68360 Quad Integrated Communications Controller (QUICC) UserÕs Manual. 18.1 Features Figure 18-1 shows a block diagram of the CPM. MOTOROLA Chapter 18. Communications Processor Module and CPM Timers 18-1...
Page 538 Ñ RISC timer tables ¥ Four full-duplex serial communications controllers (SCCs) that support the following: Ñ UART protocol (asynchronous or synchronous) Ñ HDLC protocol Ñ AppleTalk protocol Ñ Asynchronous HDLC protocol Ñ BISYNC protocol 18-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 539 ¥ Four general-purpose 16-bit timers or two 32-bit timers ¥ CPM interrupt controller (CPIC) ¥ General-purpose I/O ports Figure 18-2 shows a typical MPC860 conÞguration for a multiprotocol application that supports various communications links and protocols. MOTOROLA Chapter 18. Communications Processor Module and CPM Timers 18-3...
Page 540 RISC timer tables described in Section 19.7, ÒThe RISC Timer Table.Ó Each timer consists of the following: ¥ Timer mode register (TMR) ¥ Timer capture register (TCR) ¥ Timer counter (TCN) ¥ Timer reference register (TRR) ¥ Timer event register (TER) ¥ Timer global conÞguration register (TGCR). 18-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 541 The following subsections describe the timer operation. The timer mode registers (TMRx) and the timer global conÞguration register (TGCR) mentioned in this section are described in Section 18.2.3, ÒCPM Timer Register Set.Ó MOTOROLA Chapter 18. Communications Processor Module and CPM Timers 18-5...
Page 542 2, TGATE2 for timer 3 and/or 4. Normal gate mode enables the count on a falling edge of TGATEx and disables the count on the rising edge of TGATEx. This allows the timer to count conditionally, depending on the state of TGATEx. 18-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 543 TMR2 and TMR4 are used to deÞne the mode. Similarly, the capture is controlled by TIN2 or TIN4, and interrupts are generated by TER2 or TER4. In cascaded mode, the cascaded TRR, TCR, and TCN should always be accessed with 32-bit bus cycles. MOTOROLA Chapter 18. Communications Processor Module and CPM Timers 18-7...
Page 544 0 Restart gate mode. A falling edge of TGATE2 enables and restarts the count and a rising edge of TGATE2 disables the count. 1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE2 does not restart the count value in the TCN. 18-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 545 Free run/restart. 0 Free run. The timer count continues to increment after the reference value is reached. 1 Restart. The timer count is reset immediately after the reference value is reached. MOTOROLA Chapter 18. Communications Processor Module and CPM Timers 18-9...
Page 546 TCN1ÐTCN4 yields the current value of the timer, but does not affect the counting operation. A write cycle to TCN1ÐTCN4 sets the register to the written value, thus causing its corresponding prescaler, TMRx[PS], to be reset. 18-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 547 Output reference event. When set, indicates the counter reached the value in the TRR. TMR[ORI] is used to enable the interrupt request caused by this event. Capture event. Indicates that the counter value has been latched into the TCR. TMR[CE] enables generation of this event. MOTOROLA Chapter 18. Communications Processor Module and CPM Timers 18-11...
Page 548 7. Set CIMR = 0x0004_0000 to enable timer 2 interrupts in the CPIC and initialize the CICR. 8. Set TGCR = 0x0091 to enable timers 1 and 2 to begin counting in cascaded mode. 18-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 549 ¥ Performs lower-layer protocol processing for communication channels ¥ Protocol-processing microcode routines located in internal ROM ¥ Optional Motorola-supplied microcode packages run from dual-port RAM (The microcode packages allow the addition of protocols and other enhancements.) ¥ Digital signal processing (DSP) capability using a multiplier/accumulator (MAC) and special addressing modes ¥...
Page 550 FIFOs are 32 bytes each; SCC2ÐSCC4 FIFOs are 16 bytes each. The serial management controllers (SMCs), serial peripheral interface (SPI), and I C are all double-buffered, creating effective FIFO sizes of two characters. The parallel interface port (PIP) is a single register interface. 19-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 551 SPI Tx C Rx C Tx RISC timer table IDMA emulation: DREQ0 and DSP1 (option 3) IDMA emulation: DREQ1 and DSP2 (option 3) See the RCCR[DRQP] description in Section 19.5.1, ÒRISC Controller ConÞguration Register (RCCR).Ó MOTOROLA Chapter 19. Communications Processor 19-3...
Page 552 RAM. The CP writes a part revision number stored in ROM to a dual-port RAM location called REV_NUM that resides in the miscellaneous parameter RAM. REV_NUM determines which version of Motorola-supplied microcode package to use; see Table 19-2. Table 19-2. CP Microcode Revision Number Offset...
Page 553 01 IDMA requests have priority immediately following the SCCs (option 2). 10 IDMA requests have the lowest priority (option 3). 11 Reserved. External interrupt enable. ConÞgure as instructed in the download process of a Motorola-supplied RAM microcode package. 0 DREQ0 cannot interrupt the CP.
Page 554 Command semaphore ßag. Set by the core and cleared by the CP. 0 CP is ready to receive a new command. 1 CP is currently processing a commandÑcleared when the command is done or after reset. 19-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 555 GCI ABORT REQUEST 1011 Ñ Ñ Ñ Ñ Ñ Ñ Ñ STOP IDMA 1100 Ñ Ñ Ñ Ñ Ñ Ñ Ñ START DSP 1101 Ñ Ñ Ñ Ñ Ñ Ñ Ñ INIT DSP 111x MOTOROLA Chapter 19. Communications Processor 19-7...
Page 556 FD_PTR to the function descriptor table base address FDBASE. Start DSP chain. Activates the current chain. START DSP UndeÞned. Reserved for use by Motorola-supplied RAM microcode packages. 19.5.3.1 CP Command Examples To completely reset the CPM, write 0x8001 to the CPCR. After two clocks, the CPCR should return a 0x0000 value.
Page 557 ¥ Storing the BDs (in any unused dual-port RAM area) ¥ Storing buffers (in any unused dual-port RAM area or external memory) ¥ Storing Motorola-supplied microcode for the CP (in system RAM only) ¥ Scratchpad area for user software (in any unused dual-port RAM area) The dual-port RAM can be accessed either by the CP or by one of two internal U-bus mastersÑthe PowerPC core or an SDMA channel.
Page 558 Figure 19-5. Dual-Port RAM Memory Map 19.6.1 System RAM and Microcode Packages When optional Motorola-supplied RAM microcode packages are activated, certain portions of the system RAM are no longer available. Depending on the memory requirements of the microcode package, some or all of the shaded areas of Figure 19-5 become locked. Reads to locked areas return all ones.
Page 559 0x3C00 0x1C00Ñ0x1C7F SCC1 0x1C80Ñ0x1CAF 0x1CB0Ñ0x1CBF Miscellaneous 0x1CC0Ñ0x1CFF IDMA1 0x3D00 0x1D00Ñ0x1D7F SCC2 0x1D80Ñ0x1DAF 0x1DB0Ñ0x1DBF RISC timer table 0x1DC0Ñ0x1DFF IDMA2 0x3E00 0x1E00Ñ0x1E7F SCC3 0x1E80Ñ0x1EBF SMC1 0x1EC0Ñ0x1EFF DSP1 (Rx) 0x3F00 0x1F00Ñ0x1F7F SCC4 0x1F80Ñ0x1FBF SMC2/PIP 0x1FC0Ñ0x1FFF DSP2 (Tx) MOTOROLA Chapter 19. Communications Processor 19-11...
Page 560 TM_CNT and stops working on the timer table until the next scan tick. is issued, the CP makes the appropriate modiÞcations to the timer table and SET TIMER parameter RAM, but does not scan the timer table until the next tick of the internal CP 19-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 561 RISC timers 0 and 1 are enabled. TM_BASE should be word-aligned. 0x02 TM_PTR Hword RISC timer table pointer. Only the CP uses this register to point to the next timer accessed in the timer table. Do not modify this register. MOTOROLA Chapter 19. Communications Processor 19-13...
Page 562 Timer Number A value from 0Ð15 signifying which timer to useÑan offset into the timer table entries. 16Ð31 Timer Period The 16-bit timeout count of the timer. The maximum value is 65,536 and is programmed by writing 0x0000 to the timer period. 19-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 563 ¥ Program TM_CMD[Timer Period] to be the high period of the waveform. ¥ Set TM_CMD[V, PWM]. The second timer (odd numbered) determines the overall period: ¥ Program TM_CMD[Timer Period] to be the period of the whole waveform. ¥ Set TM_CMD[V, R] and clear TM_CMD[PWM]. MOTOROLA Chapter 19. Communications Processor 19-15...
Page 564 8. Issue by writing 0x0851 to the CPCR. SET TIMER 9. Repeat the steps 7 and 8 for each timer to be enabled or disabled. 19-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 565 1. Program RCCR[TIMEP] to 0b001111 for a table scan tick of 16 ´ (1,024) = 16,384. 2. Disable RISC timer table interrupts, if preferred. 3. Using , initialize all 16 RISC timers to have a timer period of 0x0000, SET TIMER which corresponds to 65,536. MOTOROLA Chapter 19. Communications Processor 19-17...
Page 566 RISC timer 15. If the difference between them exceeds two ticks, the CP has, during some scan tick interval, exceeded the 96% utilization level. Note that when comparing timer counts, the general-purpose timers are up-counters, while RISC timers are down-counters. 19-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 567 External System Internal U-Bus System Bus PowerPC Interface Core Unit (SIU) External Communications Dual-Port Processor SDMA (CP) SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 Figure 20-1. MPC860 SDMA Data Paths MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-1...
Page 568 Once an SDMA channel obtains the external system bus, it remains master for the whole transactionÑa byte, half-word, word or burst transferÑbefore relinquishing the bus. This feature, in combination with the zero-clock arbitration overhead provided by the U-bus, increases bus efÞciency and lowers latency. 20-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 569 U-bus priority level and freeze-signal (FRZ) behavior. It is always read/write in supervisor mode, even though writing to the SDCR is not recommended unless the CPM is disabled. Figure 20-3 shows the register format. MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-3...
Page 570 SDSR. SDSR bits are cleared by writing ones; writing zeros has no effect. Figure 20-4 shows the register format. Field SBER Ñ DSP2 DSP1 Reset 0000_0000 Addr IMMR + 0x908 Figure 20-4. SDMA Status Register (SDSR) 20-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 571 See Section 20.3.4.2, ÒAuto-Buffering and Buffer-Chaining.Ó Single-buffering is a special, low-latency IDMA transfer mode optimized for transferring one buffer from a peripheral to memory. This low-overhead mode uses single-address MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-5...
Page 572 Source data pointer (internal-use). Points to the next source byte to be read.The CP initializes SAPR to the BDÕs source buffer pointer and increments it automatically if the source is memory (DCMR[S/D] = 0bx0). 20-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 573 (cycle mode) of the IDMA channels. Figure 20-5 shows the register format. Field Ñ SIZE Reset Addr IDMAx Base + 0x02 Figure 20-5. DMA Channel Mode Register (DCMR) MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-7...
Page 574 Figure 20-6. IDMA Status Registers (IDSR1/IDSR2) Table 20-6 describes the IDSR Þelds. Table 20-6. IDSR1/IDSR2 Field Descriptions Bits Name Description 0Ð4 Ñ Reserved Auxiliary done. Set after processing a BD that has its I bit (interrupt) set. 20-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 575 ¥ The half word at (offset + 0) is the status-and-control Þeld. ¥ The byte at (offset + 2) is the destination function code register (DFCR). See Section 20.3.4.1, ÒFunction Code RegistersÑSFCR and DFCR.Ó MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-9...
Page 576 0 Not the last descriptor in the BD table. 1 Last descriptor in the BD table. After this descriptor has been processed, the CP wraps the current BD pointer (IBPTR) back to the top of the BD table (IBASE). 20-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 577 DMA type. Note that for the last IDMA cycle, the terminal count code AT[0Ð3] = 0xF replaces the user-deÞned function code signaling the end of transfer to the peripheral. MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-11...
Page 578 In the initialization phase, the core loads the global IDMA channel information into the IDMA parameter RAM, builds the IDMA BD table, and starts the channel. In the transfer phase, the CPM accepts a transfer request, 20-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 579 To use a general-purpose I/O line, follow these steps: 1. Externally connect a general-purpose output line to DREQ. 2. Set RCCR[DRnM] (level-sensitive). 3. Drive the output low when the request generation should begin. MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-13...
Page 580 Section 34.4.1.5, ÒPort C Interrupt Control Register (PCINT).Ó In edge-sensitive mode, an IDMA channel moves one data operand per request. DREQ is sampled at each rising edge of the clock. When IDMA detects a request on DREQ, the 20-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 581 DCMR[S/D] controls the direction of the transfer. If DCMR[S/D] = 0b01, the IDMA controller handshakes with the peripheral for the source data and writes to the destination memory address provided. If MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-15...
Page 582 See Section 20.3.7, ÒIDMA Interface SignalsÑDREQ and SDACK,Ó for more on IDMA handshake signals. CLKOUT Address SETUP HOLD Data SDACK DELAY PHOLD Figure 20-10. SDACK Timing Diagram: Single-Address Peripheral Write, Externally-Generated TA 20-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 583 The DAPR is incremented by 1, 2, or 4, according to the programming of DCMR[SIZE]. See Section 20.3.7, ÒIDMA Interface SignalsÑDREQ and SDACK,Ó for more on IDMA handshake signals. MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-17...
Page 584 Single-buffer mode is selected by setting RCCR[EIE], the CPM external interrupt enable bit; see Section 19.5.1, ÒRISC Controller ConÞguration Register (RCCR).Ó Note that the CPM external interrupt always refers to a special request to the CPM, not to the core. 20-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 585 IDSR1 in single-buffer mode behaves the same way as deÞned in Section 20.3.3.2, ÒIDMA Status Registers (IDSR1 and IDSR2).Ó The only relevant event bit, however, is DONE, which is set when the byte count in BCR reaches zero. Figure 20-14 shows the register format. MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-19...
Page 586 The peripheral must negate DREQ0 before the last beat of the transfer; otherwise, IDMA assumes that another DMA request is pendingÑDCMR[STR] will not be clearedÑand immediately initiates another transfer. If no buffer is available when this extra transfer begins, erratic operation occurs. 20-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 587 DCMR[S/D]. Note that if Ethernet is running, this method does not work since SCCs in Ethernet mode also toggle SDACK for SDMA transfers. MOTOROLA Chapter 20. SDMA Channels and IDMA Emulation 20-21...
Page 588 TEA to detect a bus exception for the current bus cycle. TEA terminates the cycle immediately and negates SDACK, which is used to control the transfer to or from the device. 20-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 589 If the TSA is not required for routing data to and from the SCCs and SMCs, it can still be used to generate complex waveforms on its four strobe output pins (L1ST1Ð4). For example, the user can program the TSA to implement stepper motor control signals of variable duty cycle and period. MOTOROLA Chapter 21. Serial Interface 21-1...
Page 590 SCC1 SCC2 SCC3 SCC4 Time-Slot Assigner TDM a&b TDM a&b SMC1 SMC2 SCC1 SCC2 SCC3 SCC4 Strobes Pins Pins Pins Pins Pins Pins Pins Non-multiplexed Serial Interface (NMSI) Figure 21-1. MPC860 SI Block Diagram 21-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 591 (TDM) for multiplexed serial channels. The TSA supports the serial bus rate and format for most standard TDM buses, including the T1 and CEPT highways, pulse code modulation (PCM) highway, and ISDN buses in both basic and primary rates. The two MOTOROLA Chapter 21. Serial Interface 21-3...
Page 592 For more ßexibility, the user can also provide separate Rx and Tx syncs as well as independent clocks. Figure 21-2 shows example TSA conÞgurations ranging from the simplest to the most complex. 21-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 593 Most Complex TDM Example Ð Totally Independent Rx and Tx MPC860 TDM Tx Sync TDM Tx Clk SCC2 SMC1 SCC2 TDM Tx TDM Rx Sync TDM Rx Clk TDM Rx SCC2 SMC1 Figure 21-2. Various Configurations of a TDM Channel MOTOROLA Chapter 21. Serial Interface 21-5...
Page 594 The TSA routing is programmed in a 512-byte, core-accessible SI RAM located in the internal register section of the MPC860 separate from the dual-port RAM. The SI RAM contains a total of 128 32-bit entries: the Þrst 64 entries are for programming receive 21-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 595 Transmit data. Open-drain output of the MPC860. L1CLKOx Clock output (optional). Output from the MPC860. Needed only for clocking external devices in GCI mode. L1RQx/L1GRx IDL request (output) and grant (input) signals. Used if D-channel arbitration is required. MOTOROLA Chapter 21. Serial Interface 21-7...
Page 596 The SI RAM totals 128 32-bit entriesÑ64 entries each for receive and transmit routing. Representing one time slot, an entry controls from 1 to 16 bits/bytes and up to four strobe pins (all active high). 21-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 597 One Channel (TDMa) with Independent Rx and Tx Route Framing Signals SI RAM Address: L1RCLKa (32-Bit Entries) 64 Entries L1RSYNCa Route L1TCLKa 64 Entries L1TSYNCa Route Figure 21-5. SI RAM Partitioning Using TDMa with Static Frames MOTOROLA Chapter 21. Serial Interface 21-9...
Page 598 When using only one channel (TDMa) with dynamic changes, as in Figure 21-7, the initial current-route RAM byte addresses are as follows. ¥ 0Ð127 RXa route ¥ 256Ð383 TXa route The shadow RAMs are at addresses: ¥ 128Ð255 RXa route ¥ 384Ð511 TXa route 21-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 599 ¥ 0Ð63 RXa route ¥ 128Ð191 RXb route ¥ 256Ð319TXa route ¥ 384Ð447 TXb route The shadow RAMs are at addresses: ¥ 64Ð127 RXa route ¥ 192Ð255 RXb route ¥ 320Ð383 TXa route ¥ 448Ð511TXb route MOTOROLA Chapter 21. Serial Interface 21-11...
Page 600 RAM. The SI RAM pointer (SIRP) register can be used to determine which SI RAM entry is active. In addition, by externally connecting a strobe to an interrupt signal, an individual SI RAM entry can generate an interrupt. 21-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 601 16 Entries 16 Entries L1RCLKa L1RCLKb L1RSYNCa L1RSYNCb Route Route Shadow Shadow 16 Entries 16 Entries L1TCLKa L1TCLKb L1TSYNCa L1TSYNCb Route Route Shadow Shadow Figure 21-9. SI RAM Partitioning Using Two TDMs with Dynamic Frames MOTOROLA Chapter 21. Serial Interface 21-13...
Page 602 000 This time slot is not used. Tx data signal is three-stated; Rx data signal is ignored. 001 SCC1 010 SCC2 011 SCC3 100 SCC4 101 SMC1 110 SMC2 111 This time slot is not used. Also used in SCIT mode to indicate the D channel grant bit. 21-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 603 SCC3, the Þrst 4 bits of the B2 channel with an external device (using a strobe to enable the external device), and the last 4 bits of B2 with SMC1. Additionally, the TSA marks the D channel with another strobe signal. MOTOROLA Chapter 21. Serial Interface 21-15...
Page 604 The following sections describe the SI registers. 21.2.4.1 SI Global Mode Register (SIGMR) The SI global mode register (SIGMR), shown in Figure 21-12, deÞnes the SI RAM division modes and enables the individual TDM channels. 21-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 605 SCC. 21.2.4.2 SI Mode Register (SIMODE) The SI mode register (SIMODE), shown in Figure 21-13, deÞnes the SI operation modes for the TDM channels and SMCs. MOTOROLA Chapter 21. Serial Interface 21-17...
Page 606 11 Loopback control. TDM transmitter output is connected internally to the TDM receiver inputÑ L1TXDx is connected to L1RXDx. Transmitter output L1TXDx and L1RQx are inactive. Provides loopback testing of the entire TDM without affecting the external serial lines. 21-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 607 Note that for the MPC860 Rev. B and later, if GMb = 1, then the RTS3 signal on ports B and C functions as L1RQB. (The RTS3 function is still available on port D.) MOTOROLA Chapter 21. Serial Interface 21-19...
Page 608 No Delay from Sync Latch to First Bit of Frame Figure 21-15. No Delay from Sync to Data (xFSD = 00) Figure 21-16 and Figure 21-17 show example timings while changing SIMODE[DSC] and SIMODE[CE]. 21-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 609 L1ST in Both the FE Settings (On Bit-0) Rx Sampled Here Figure 21-17. Clock Edge (CE) Effect when DSC = 1 Figure 21-18 shows SIMODE[FE] behavior with SIMODE[CE] set and no frame sync delay. MOTOROLA Chapter 21. Serial Interface 21-21...
Page 610 L1ST and Data Bit-0 is Driven L1ST from Clock Low. (On Bit-0) Figure 21-18. Frame Transfers when xFSD = 0 and CE = 1 Figure 21-19 shows SIMODE[FE] behavior when SIMODE[CE] and SIMODE[xFSD] are zero. 21-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 611 The SI clock route register (SICR), shown in Figure 21-20, selects the SCC clock source from one of four baud rate generators or an input from the bank of clock pins. The SICR also connects the SCCs to the TSA and enables the grant mechanism chosen in SIMODE. MOTOROLA Chapter 21. Serial Interface 21-23...
Page 612 The SI command register (SICMR) is used to swap the SI RAM routing. SICMR commands are valid only when the SI RAM is partitioned for dynamic changes; that is, when SIGMR[RDM] = 0b01 or 0b11. See Section 21.2.3.4, ÒSI RAM Dynamic Changes.Ó 21-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 613 Address of the current route of TDMa transmitter. 0 Address 256Ð383 when SIGMR[RDM] = 01. Address 256Ð319 when SIGMR[RDM] = 11. 1 Address 384Ð511 when SIGMR[RDM] = 01. Address 320Ð383 when SIGMR[RDM] = 11. MOTOROLA Chapter 21. Serial Interface 21-25...
Page 614 The pointers in SIRP indicate the SI RAM entry word offset that is in progress. Field Ñ TbPTR Ñ TaPTR Reset Addr 0XAF0 Field Ñ RbPTR Ñ RaPTR Reset Addr 0xAF2 Figure 21-23. SI RAM Pointer Register (SIRP) 21-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 615 ¥ TbPTR points to the active TXb entry. If TbPTR = 0Ð15, the current-route RAM is SI RAM address block 384Ð447 and SISTR[CROTb] = 0. If TbPTR = 16Ð31, the current-route RAM is SI RAM address block 448Ð511 and SISTR[CROTb] = 1. MOTOROLA Chapter 21. Serial Interface 21-27...
Page 616 CODEC as a digital voice channel, if preferred. The SPI is used to send initialization commands and periodically check status from the S/T transceiver. The SMC connected to the terminal is conÞgured for UART. 21-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 617 ¥ D is a 16-Kbps signaling channel There are two deÞnitions of the IDL bus frame structureÑ8- and 10-bit. The only difference between them is the channel order within the frame. See Figure 21-26. MOTOROLA Chapter 21. Serial Interface 21-29...
Page 618 IDL control channel would be out-of-band. These functions were deÞned as a subset of the Motorola SPI format called serial control port (SCP). To implement the A and M bits as originally deÞned, program the TSA to access these bits and route them transparently to an SCC or SMC.
Page 619 0000 0000 1 bit no support 0000 0000 8 bits SMC2 (B2) 0001 0000 1 bit SCC3 (D) and strobe1 2. SIMODE = 0x8000_0145. Only TDMa is used. SMC2 is connected to the TSA. MOTOROLA Chapter 21. Serial Interface 21-31...
Page 620 ¥ L1RXDxÑUsed as a GCI receive data. Input to the MPC860. ¥ L1TXDxÑUsed as a GCI transmit data. Open-drain output. Driven only for the bits that are programmed in the SI RAM. Otherwise, it is three-stated. 21-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 621 D channel and indicates on this bit that the channel is free. If a collision is detected on the D channel, the physical layer device drives bit 4 of C/I MOTOROLA Chapter 21. Serial Interface...
Page 622 This bit is sampled by the SI and transferred to the D-channel SCC as the grant. The grant is generally bit 4 of the C/I in channel 2 of the GCI bus, but any bit slot can be selected in the SI RAM. 21-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 623 11. SISTR and SIRP do not need to be read but can be used for debugging when channels are enabled. 12. Enable SCC3 for HDLC operation (to handle the LAPD protocol of the D channel), conÞgure SCC2 and SMC2 as needed and enable SMC1 for SCIT operation. MOTOROLA Chapter 21. Serial Interface 21-35...
Page 624 RCLKx and TCLKx can be used as inputs to the DPLL unit, which is inside the SCCx; thus, RCLKx and TCLKx are not always required to reßect the actual bit rate on the line. The signals available to each SCC and SMC in NMSI mode are shown in Figure 21-28. 21-36 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 625 ¥ CD1 The SCC2 in NMSI mode has its own set of modem control signals: ¥ TXD2 ¥ RXD2 ¥ TCLK2 ¬ BRG1ÐBRG4, CLK1ÐCLK4 ¥ RCLK2 ¬ BRG1ÐBRG4, CLK1ÐCLK4 ¥ RTS2 ¥ CTS2 ¥ CD2 MOTOROLA Chapter 21. Serial Interface 21-37...
Page 626 ¥ SMTXD2 ¥ SMRXD2 ¥ SMCLK2 ¬ BRG1ÐBRG4, CLK5ÐCLK8 ¥ SMSYN2 (used only in the totally transparent protocol) Unused SCC or SMC signals can be used for other functions or conÞgured for parallel I/O. 21-38 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 627 Additionally, CLK2 and CLK6 allow a single external frequency to be the source for multiple BRGs. Note that the CLK2 and CLK6 signals are not synchronized internally before being used by the BRG. MOTOROLA Chapter 21. Serial Interface 21-39...
Page 628 Reset BRG. Performs a software reset of the BRG identical to that of an external reset. A reset disables the BRG and drives BRGO high. This is externally visible only if BRGO is connected to the corresponding parallel I/O pin. 0 Enable the BRG. 1 Reset the BRG (software reset). 21-40 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 629 After a full character is received, the software can verify that the character matches a predeÞned value (such as ÔaÕ or ÔAÕ). Software should then check for other characters (such as ÔtÕ or ÔTÕ) and program the preferred parity mode in the UARTÕs protocol-speciÞc mode register (PSMR). MOTOROLA Chapter 21. Serial Interface 21-41...
Page 630 1040 75.05 1301 1279 149.954 300.48 300.5 2082 600.09 2603 2559 1200 1040 1200.7 1301 1200 1279 1200 2400 2399.2 2400.1 2400 4800 4807.7 4807.69 4800 9600 9615.4 9585.9 9600 19200 19231 19290 19200 21-42 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 631 = (BRGCLK or CLK2 or CLK6) ¸ (1 or 16 according to BRGCx[DIV16]) ¸ (clock divider + 1) For example, to get a rate of 64 Kbps, the system clock can be 24.96 MHz, DIV16 = 0, and the clock divider = 389. MOTOROLA Chapter 21. Serial Interface 21-43...
Page 632 Part V. The Communications Processor Module 21-44 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 633 (For example, an SCC internal clock can run at 12.5 MHz in a 25-MHz system.) However, an SCCÕs ability to support a sustained bit stream depends on the protocol as well as other factors. See Appendix B, ÒSerial Communications Performance.Ó MOTOROLA Chapter 22. Serial Communications Controllers 22-1...
Page 634 ¥ Supports 10-Mbps Ethernet/IEEE 802.3 (half- or full-duplex) ¥ Additional protocols supported through Motorola-supplied RAM microcodes: ProÞbus, Signaling System#7 (SS7), ATM over T1/E1 (ATOM1) ¥ Additional protocols can be added in the future through the use of RAM microcodes.
Page 635 Each SCC contains a general SCC mode register (GSMR) that deÞnes options common to each SCC regardless of the protocol. GSMR_L contains the low-order 32 bits; GSMR_H, shown in Figure 22-2, contains the high-order 32 bits. Some GSMR operations are described in later sections. MOTOROLA Chapter 22. Serial Communications Controllers 22-3...
Page 636 1 Reverses the bit order for totally transparent channels on this SCC (either the receiver, transmitter, or both) and sends the msb of each byte Þrst. Section 27.11, ÒBISYNC Mode Register (PSMR),Ó describes reversing bit order in a BISYNC protocol. 22-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 637 CTS is asserted to the SCC. Assuming CTS is asserted, transmission begins 8 clocks after the receiver starts receiving data. MOTOROLA Chapter 22. Serial Communications Controllers 22-5...
Page 638 0xA00 (GSMR_L1), 0xA20 (GSMR_L2), 0xA40 (GSMR_L3), 0xA60 (GSMR_L4) Field RDCR RENC TENC DIAG ENR ENT MODE Reset Addr 0xA02 (GSMR_L1), 0xA22 (GSMR_L2), 0xA42 (GSMR_L3), 0xA62 (GSMR_L4) Figure 22-3. GSMR_LÑGeneral SCC Mode Register (Low Order) 22-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 639 010 16 bits (2 bytes). 011 32 bits (4 bytes). 100 48 bits (6 bytes). Select this setting for Ethernet operation. 101 64 bits (8 bytes). 110 128 bits (16 bytes). 111 Reserved. MOTOROLA Chapter 22. Serial Communications Controllers 22-7...
Page 640 000 NRZ (default setting if DPLL is not used). Required for UART (synchronous or asynchronous). 001 NRZI Mark (set RINV/TINV also for NRZI space). 010 FM0 (set RINV/TINV also for FM1). 011 Reserved. 100 Manchester. 101 Reserved. 110 Differential Manchester (Differential Bi-phase-L). 111 Reserved. 22-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 641 0011 SS7Ñreserved for RAM microcode 0100 UART 0101 ProÞbusÑreserved for RAM microcode 0110 Asynchronous HDLC or IrDA 0111 V.14Ñreserved for RAM microcode 1000 BISYNC 1001 DDCMPÑreserved for RAM microcode 101x Reserved 1100 Ethernet 11xx Reserved MOTOROLA Chapter 22. Serial Communications Controllers 22-9...
Page 642 Tx buffer/frame and is useful in LAN-type protocols where maximum interframe gap times are limited by the protocol speciÞcation. Field Ñ Reset Addr 0xA0C (TODR1), 0xA2C (TODR2), 0xA4C (TODR3), 0xA6C (TODR4) Figure 22-5. Transmit-on-Demand Register (TODR) 22-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 643 Ñ For a TxBD, this is the number of bytes the controller should send from its buffer. Normally, this value should be greater than zero. The CP never modiÞes this Þeld. MOTOROLA Chapter 22. Serial Communications Controllers 22-11...
Page 644 Figure 22-7 shows the SCC BD table and buffer structure. 22-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 645 BD. If E = 0, the current buffer is not empty and it reports a busy error. The CP does not move from the current BD until E is set by the MOTOROLA Chapter 22. Serial Communications Controllers...
Page 646 Values in RBASE and TBASE should be multiples of eight. 0x04 RFCR Byte Rx function code. See Section 22.3.1, ÒFunction Code Registers (RFCR and TFCR).Ó 0x05 TFCR Byte Tx function code. See Section 22.3.1, ÒFunction Code Registers (RFCR and TFCR).Ó 22-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 647 From SCC base. SCC base = IMMR + 0x3C00 (SCC1) or 0x3D00 (SCC2) or 0x3E00 (SCC3) or 0x3F00 (SCC4) These parameters need not be accessed for normal operation but may be helpful for debugging. For CP use only MOTOROLA Chapter 22. Serial Communications Controllers 22-15...
Page 648 To allow interrupt handling for SCC-speciÞc events, further event, mask, and status registers are provided within each SCCÕs internal memory map area; see Table 22-6. Since interrupt events are protocol-dependent, event descriptions are found in the speciÞc protocol chapters. 22-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 649 1. Write the parallel I/O ports to conÞgure and connect the I/O pins to the SCCs. 2. Set the SDMA conÞguration register SDCR[RAID] Þeld to 0b01 (U-bus arbitration priority level 5). 3. ConÞgure the parallel I/O registers to enable RTS, CTS, and CD if these signals are required. MOTOROLA Chapter 22. Serial Communications Controllers 22-17...
Page 650 GSMR_H[CTSS]. This operation assumes that CTS is already asserted to the SCC or that CTS is reprogrammed to be a parallel I/O line, in which case CTS to the SCC is always asserted. RTS is negated one clock after the last bit in the frame. 22-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 651 CTS lost error. Negating CTS forces RTS high and Tx data to become idle. If GSMR_H[CTSS] is zero, the SCC must sample CTS before a CTS lost is recognized; otherwise, the negation of CTS immediately causes the CTS lost condition. See Figure 22-11. MOTOROLA Chapter 22. Serial Communications Controllers 22-19...
Page 652 Reception delays are determined by CD as shown in Figure 22-12. If GSMR_H[CDS] is zero, CD is sampled on the rising Rx clock edge before data is received. If GSMR_H[CDS] is 1, CD transitions cause data to be immediately gated into the receiver. 22-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 653 ¥ If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 0, transmission begins in three additional bit times. ¥ If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 1, transmission begins in two additional bit times. MOTOROLA Chapter 22. Serial Communications Controllers 22-21...
Page 654 RDCR Recovered Clock HSRCLK RCLK Carrier SNC EDGE DPLL Noise TSNC Receiver Hunting RINV 1x Mode Decoded Data HSRCLK RINV SCCR Data RENC ¹ NRZI 1x Mode HSRCLK Figure 22-13. DPLL Receiver Block Diagram 22-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 655 DPLL should receive a preamble pattern before it receives the data. In some protocols, the preceding ßags or syncs can function as a preamble; others use the patterns in Table 22-7. When transmission occurs, the SCC can generate preamble patterns, as programmed in GSMR_L[TPP, TPL]. MOTOROLA Chapter 22. Serial Communications Controllers 22-23...
Page 656 Each SCC contains a DPLL unit that can be programmed to encode and decode the SCC data as NRZ, NRZI Mark, NRZI Space, FM0, FM1, Manchester, and Differential Manchester. Figure 22-15 shows the different encoding methods. 22-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 657 22.3.6 Clock Glitch Detection Clock glitches cause problems for many communications systems, and they may go undetected by the system. Systems that supply an external clock to a serial channel are often MOTOROLA Chapter 22. Serial Communications Controllers 22-25...
Page 658 4. If an command was not issued in step 3, issue a INIT TX PARAMETERS RESTART command. TRANSMIT 5. Set GSMR_L[ENT]. Transmission begins using the TxBD pointed to by TBPTR, assuming the R bit is set. 22-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 659 RX PARAMETERS 3. Set GSMR_L[ENT, ENR] to enable the SCC with the new protocol. 22.3.8 Saving Power To save power when not in use, an SCC can be disabled by clearing GSMR_L[ENT, ENR]. MOTOROLA Chapter 22. Serial Communications Controllers 22-27...
Page 660 Part V. The Communications Processor Module 22-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 661 RS-485, which deÞnes a balanced line system allowing longer cables than RS-232 links. Even synchronous protocols like HDLC are sometimes deÞned to run over asynchronous links. The ProÞbus standard extends UART protocol to include LAN-oriented features such as token passing. MOTOROLA Chapter 23. SCC UART Mode 23-1...
Page 662 ¥ Received break character length indication ¥ Programmable data length (5Ð8 bits) ¥ Programmable fractional stop bit lengths (from 9/16 to 2 bits) in transmission ¥ Capable of reception without a stop bit ¥ Even/odd/force/no parity generation and check 23-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 663 FIFO before proceeding to the receive buffer. The CPM ßags UART events, including reception errors, in SCCE and the RxBD status and control Þelds. GSMR_H[RFW] must be set for an 8-bit receive FIFO. MOTOROLA Chapter 23. SCC UART Mode 23-3...
Page 664 XOFF and XON, into the transmit stream. The TOSEQ character is put in the Tx FIFO without affecting a Tx buffer in progress. See Section 23.11, ÒInserting Control Characters into the Transmit Data Stream.Ó 23-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 665 When receiving messages, up to eight control characters can be conÞgured to mark the end of a message or generate a maskable interrupt without being stored in the buffer. This option MOTOROLA Chapter 23. SCC UART Mode 23-5...
Page 666 Resets the receive parameters in the parameter RAM. Should be issued when the receiver is disabled. INIT RX Note that resets both Tx and Rx parameters. PARAMETERS INIT TX AND RX PARAMETERS 23-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 667 UART parameter RAM. Each incoming character is compared to the table entries using a mask (the received control character mask, RCCM) to strip donÕt cares. If a match occurs, the received control character can either be written to the receive buffer or rejected. MOTOROLA Chapter 23. SCC UART Mode 23-7...
Page 668 SCCE[CCR]. The current Rx buffer is not closed. 2Ð7 Ñ Reserved 8Ð15 CHARACTERn Control character values 1Ð8. DeÞnes control characters to be compared to the incoming character. For characters smaller than 8 bits, the most signiÞcant bits should be zero. 23-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 669 FIFO. This means that the XON or XOFF character may not be sent for eight (SCC1) or four (SCC2ÐSCC4) character times. To reduce this latency, set GSMR_H[TFL] to decrease the FIFO size to one character before enabling the transmitter. MOTOROLA Chapter 23. SCC UART Mode 23-9...
Page 670 For example, for 8 data bits, no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones is sent before the Þrst character in the buffer. 23-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 671 The UART receiver can always receive fractional stop bits. The next characterÕs start bit can begin any time after the three middle samples have been taken. 5Ð6 Ñ 0b11 7Ð8 Ñ 0b00 9Ð14 Ñ 0b111111 Ñ MOTOROLA Chapter 23. SCC UART Mode 23-11...
Page 672 Rx buffer, sets RxBD[BR], and sets SCCE[RX], which can generate an interrupt if not masked. If PSMR[RZS] = 1 when the UART is in synchronous mode, a break sequence is detected after two successive break characters are received. 23-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 673 10 Reserved. 11 Automatic multidrop mode. The CPM compares the address of an incoming address character with UADDRx parameter RAM values; subsequent data is accepted only if a match occurs. MOTOROLA Chapter 23. SCC UART Mode 23-13...
Page 674 11 High parity (mark parity). The transmitter sends a one in the parity bit position. If the receiver does not read a 1 in the parity bit, a parity error is reported. 23-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 675 ¥ An address character is received in multidrop mode. The address character is written to the next buffer for a software comparison. Figure 23-7 shows an example of how RxBDs are used in receiving. MOTOROLA Chapter 23. SCC UART Mode 23-15...
Page 676 Idle Count Expires Still in Progress (MAX_IDL) with this Buffer 10 Characters 5 Characters Long Idle Period Characters Received by UART Fourth Character Present Time has Framing Error! Time Figure 23-7. SCC UART Receiving using RxBDs 23-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 677 PSMR[UM]. After an address match, AM identiÞes which user-deÞned address character was matched. 0 The address matched the value in UADDR2. 1 The address matched the value in UADDR1. Ñ Reserved, should be cleared. MOTOROLA Chapter 23. SCC UART Mode 23-17...
Page 678 1 Last BD in the table. After this buffer is used, the CPM sends data using the BD pointed to by TBASE. The number of TxBDs in this table is determined only by the W bit and space constraints of the dual-port RAM. 23-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 679 SCCE. Setting a mask bit enables the corresponding SCCE interrupt; clearing a bit masks it. Figure 23-10 shows example interrupts that can be generated by the SCC UART controller. MOTOROLA Chapter 23. SCC UART Mode 23-19...
Page 680 Ñ Ñ GRA BRKE BRKS Ñ CCR BSY Reset 0000_0000_0000_0000 Addr 0xA10 (SCCE1)/0xA14 (SCCM1); 0xA30 (SCCE2)/0xA34 (SCCM2) 0xA50 (SCCE3)/0xA54 (SCCM3); 0xA70 (SCCE4)/0xA74 (SCCM4) Figure 23-11. SCC UART Event Register (SCCE) and Mask Register (SCCM) 23-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 681 RXD. The real-time status of CTS and CD is part of the port C parallel I/O. Field Ñ Reset 0000_0000_0000_0000 Addr 0xA17 (SCCS1), 0xA37 (SCCS2), 0xA57 (SCCS3), 0xA77 (SCCS4) Figure 23-12. SCC Status Register for UART Mode (SCCS) MOTOROLA Chapter 23. SCC UART Mode 23-21...
Page 682 STOP TRANSMIT 13. Clear PAREC, FRMEC, NOSEC, and BRKEC in parameter RAM. 14. Clear UADDR1 and UADDR2. They are not used. 15. Clear TOSEQ. It is not used. 23-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 683 S-record Þts into a single buffer. Follow the basic UART initialization sequence above in Section 23.21, ÒSCC UART Programming Example,Ó except allow for more and larger buffers and create the control character table as described in Table 23-14. MOTOROLA Chapter 23. SCC UART Mode 23-23...
Page 684 TxBD table; transmission can be paused when an XOFF character is received. This scheme minimizes the number of interrupts the core receives (one per S-record) and relieves it from continually scanning for control characters. 23-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 685 TDM channels of the serial interface (SI). In HDLC mode, an SCC becomes an HDLC controller, and consists of separate transmit and receive sections whose operations are asynchronous with the core and can either be synchronous or asynchronous with respect to other SCCs. MOTOROLA Chapter 24. SCC HDLC Mode 24-1...
Page 686 When the SCC receives a STOP command, it sends idles or ßags instead of the current frame until it receives a TRANSMIT command. The command can be used to RESTART TRANSMIT GRACEFUL STOP TRANSMIT 24-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 687 Rx FIFO delay. 24.4 SCC HDLC Parameter RAM For HDLC mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in Table 24-1. MOTOROLA Chapter 24. SCC HDLC Mode 24-3...
Page 688 0xFFFF. For 8-bit addresses, clear the eight high-order HMASK bits. See Figure 24-2. 0x58 Hword Temporary storage. 0x5A TMP_MB Hword Temporary storage. From SCC base. SCC base = IMMR + 0x3C00 (SCC1) or 0x3D00 (SCC2) or 0x3E00 (SCC3) or 0x3F00 (SCC4) 24-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 689 The transmitter resumes from the current BD. Resets the Tx parameters in the parameter RAM. Issue only when the transmitter is disabled. INIT TX INIT TX AND resets both Tx and Rx parameters. PARAMETERS RX PARAMETERS MOTOROLA Chapter 24. SCC HDLC Mode 24-5...
Page 690 Frame generates the RXF interrupt if not masked. The rest of the frame is lost and other errors are not Reception checked in that frame. At this point, the receiver enters hunt mode. 24-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 691 10 32-bit CCITT-CRC (Ethernet and HDLC). X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1. MOTOROLA Chapter 24. SCC HDLC Mode...
Page 692 The CPM uses the RxBD, shown in Figure 24-5, to report on data received for each buffer. Offset + 0 Ñ Ñ Ñ Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 24-5. SCC HDLC Receive Buffer Descriptor (RxBD) 24-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 693 Carrier detect lost (NMSI mode only). Set when CD is negated during frame reception. Data length and buffer pointer Þelds are described in Section 22.2, ÒSCC Buffer Descriptors (BDs).Ó Because HDLC is a frame-based protocol, RxBD[Data Length] of the MOTOROLA Chapter 24. SCC HDLC Mode 24-9...
Page 694 Present Time Occurs before Time Legend: Closing Flag F = Flag A = Address Byte C = Control Byte I = Information Byte CR = CRC Byte Figure 24-6. SCC HDLC Receiving using RxBDs 24-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 695 CTS lost. Indicates when CTS in NMSI mode or layer 1 grant is lost in GCI or IDL mode during frame transmission. If data from more than one buffer is currently in the FIFO when this error occurs, the HDLC writes CT in the current BD after sending the buffer. MOTOROLA Chapter 24. SCC HDLC Mode 24-11...
Page 696 Set immediately if no frame was in progress when the command was issued. 9Ð10 Ñ Reserved, should be cleared. Tx error. Indicates an error (CTS lost or underrun) has occurred on the transmitter channel. 24-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 697 2. Example shows one additional opening ßag. This is programmable. 3. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself. Figure 24-9. SCC HDLC Interrupt Event Example MOTOROLA Chapter 24. SCC HDLC Mode 24-13...
Page 698 1 Set when RXD is a logic 1 (idle) for 15 or more consecutive bit times. It is cleared after a single logic 0 is received. 24.13 SCC HDLC Programming Examples The following sections show examples for programming SCCs in HDLC mode. The Þrst example uses an external clock. The second example implements Manchester encoding. 24-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 699 19. Initialize the TxBD. Assume the Tx data frame is at 0x0000_2000 in main memory and contains Þve 8-bit characters. TxBD[Status and Control] = 0xBC00, TxBD[Data Length] = 0x0005, and TxBD[Buffer Pointer] = 0x0000_2000. 20. Write 0xFFFF to SCCE to clear any previous events. MOTOROLA Chapter 24. SCC HDLC Mode 24-15...
Page 700 The HDLC bus is based on techniques used in the CCITT ISDN I.430 and ANSI T1.605 standards for D-channel point-to-multipoint operation over the S/T interface. However, the HDLC bus does not fully comply with I.430 24-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 701 Figure 24-11 shows the most common HDLC bus LAN conÞguration, a multimaster conÞguration. A station can transfer data to or from any other LAN station. Transmissions are half-duplex, which is typical in LANs. MOTOROLA Chapter 24. SCC HDLC Mode 24-17...
Page 702 Þrst transmit its data to the master, where the data is buffered in RAM and then resent to the other slave. The beneÞt of this conÞguration, however, is that full-duplex operation can be obtained. In a point-to-multipoint environment, this is the preferred conÞguration. Figure 24-12 shows the single-master conÞguration. 24-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 703 Tx clock. If the transmitted bit matches the received CTS bus sample, transmission continues. However, if the received CTS sample is 0 and the transmitted bit is 1, transmission stops after that bit and waits for an idle line before attempting retransmission. MOTOROLA Chapter 24. SCC HDLC Mode 24-19...
Page 704 Because it uses a wired-OR conÞguration, HDLC bus performance is limited by the rise time of the one bit. To increase performance, give the one bit more rise time by using a clock that is low longer than it is high, as shown in Figure 24-14. 24-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 705 If the transmission line driver has a one-bit delay, the delayed RTS can be used to enable the output of the line driver. As a result, the electrical effects of collisions are isolated locally. Figure 24-16 shows RTS timing. MOTOROLA Chapter 24. SCC HDLC Mode 24-21...
Page 706 CTS pin, it must be conÞgured in port C to connect to the chosen SCC. Because the SCC only receives clocks during its time slot, CTS is sampled only during the Tx clock edges of the particular SCC time slot. 24-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 707 24.14.6.2 HDLC Bus Controller Programming Example Except for the above discussion in Section 24.14.6.1, ÒProgramming GSMR and PSMR for the HDLC Bus Protocol,Ó use the example in Section 24.13.1, ÒSCC HDLC Programming Example #1.Ó MOTOROLA Chapter 24. SCC HDLC Mode 24-23...
Page 708 Part V. The Communications Processor Module 24-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 709 0Ð600 data bytes. Next, two bytes of CRC (the common 16-bit CRC-CCITT polynomial referenced in the HDLC standard protocol) are sent. The LocalTalk frame is then terminated by a ßag and a restricted HDLC abort sequence. Then the transmitterÕs driver is disabled. MOTOROLA Chapter 25. SCC AppleTalk Mode 25-1...
Page 710 ¥ Automatic postamble transmission ¥ Reception of sync sequence does not cause extra SCCE[DCC] interrupts ¥ Reception is automatically disabled while sending a frame ¥ Transmit-on-demand feature expedites frames ¥ Connects directly to an RS-422 transceiver 25-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 711 I/O. This causes CD and CTS to be internally asserted to the SCC. 3. Set RDCR and TDCR to (0b10) a 16´ clock. 4. Set the TENC and RENC bits to 0b010 (FM0). MOTOROLA Chapter 25. SCC AppleTalk Mode 25-3...
Page 712 Use the transmit-on-demand (TODR) register to expedite a transmit frame. See Section 22.1.4, ÒTransmit-on-Demand Register (TODR).Ó 25.4.4 SCC AppleTalk Programming Example Except for the previously discussed register programming, use the example in Section 24.13.1, ÒSCC HDLC Programming Example #1.Ó 25-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 713 ¥ Programmable opening flag, closing flag, and control escape characters ¥ Automatic transmission of the abort sequence after a command STOP TRANSMIT ¥ Automatic transmission of idle characters between frames and between characters MOTOROLA Chapter 26. SCC Asynchronous HDLC Mode and IrDA 26-1...
Page 714 The receiver decodes the transparency character required by asynchronous HDLC protocol as described in Section 26.5, ÒReceiver Transparency Decoding.Ó When the frame ends, the controller checks the incoming CRC Þeld and writes it to the buffer. The controller then 26-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 715 (0x7D) and exclusive-ORing the following byte with 0x20 before performing the CRC calculation and writing the byte into memory. Figure 26-2 shows the algorithm because some cases are not covered by RFC 1549. MOTOROLA Chapter 26. SCC Asynchronous HDLC Mode and IrDA 26-3...
Page 716 Ñ Break sequence ¥ If an invalid sequence(0x7D7D) is received, the Þrst control escape character is discarded, and the second is unconditionally XORed with 0x20. The sequence is thus stored in the buffer as 0x5D. 26-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 717 Hword End-of-ßag character. Initialize to PPP-0x7E, IrLAP-0xC1. 0x40 Hword Control escape character. Initialize to 0x7D for both PPP and IrLAP. 0x42 Ñ Word Reserved 0x46 ZERO Hword Clear this Þeld. MOTOROLA Chapter 26. SCC Asynchronous HDLC Mode and IrDA 26-5...
Page 718 General SCC parameters can be conÞgured as described in Chapter 22, ÒSerial Communications Controllers,Ó except for the following changes: 26.9.1 General SCC Mode Register (GSMR) Table 26-2 shows asynchronous HDLC-speciÞc information for the GSMR. 26-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 719 GSMR, the transmitter starts polling the Þrst BD in the TxBD table every 8 transmit clocks, or immediately if TODR[TOD] = 1, and begins sending data if TxBD[R] is set. MOTOROLA Chapter 26. SCC Asynchronous HDLC Mode and IrDA 26-7...
Page 720 Error Description CTS Lost during The channel stops sending the buffer, closes it, sets SCCE[TXE] and TxBD[CT]. The channel Frame Transmission resumes sending from the next TxBD after a command is issued. RESTART TRANSMIT 26-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 721 BRKE BRKS TXE RXF BSY TXB RXB Reset Addr 0xA10 (SCCE1)/0xA14 (SCCM1); 0xA30 (SCCE2)/0xA34 (SCCM2) 0xA50 (SCCE3)/0xA54 (SCCM3); 0xA70 (SCCE4)/0xA74 (SCCM4) Figure 26-4. Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC Mask Register (SCCM) MOTOROLA Chapter 26. SCC Asynchronous HDLC Mode and IrDA 26-9...
Page 722 RXD. The real-time status of CTS and CD is part of the port C parallel I/O. Field Ñ Reset 0000_0000_0000_0000 Addr 0xA17 (SCCS1), 0xA37 (SCCS2), 0xA57 (SCCS3), 0xA77 (SCCS4) Figure 26-5. SCC Status Register for Asynchronous HDLC Mode (SCCS) Table 26-8 describes asynchronous HDLC SCCS Þelds. 26-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 723 26.14 SCC Asynchronous HDLC RxBDs The CPM uses the RxBD, shown in Figure 26-7, to report on received data. An example of the RxBD process is shown in Figure 26-2. MOTOROLA Chapter 26. SCC Asynchronous HDLC Mode and IrDA 26-11...
Page 724 Reserved, should be cleared. Rx abort sequence. Set when an abort sequence or framing error terminates a frame. Rx CRC error. Set when a frame has a CRC error. Received CRC bytes are written to the buffer. 26-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 725 0 Not the last buffer in the current frame. 1 Last buffer in the current frame. The proper CRC and closing ßag are sent after the last byte. Ñ Reserved, should be cleared. MOTOROLA Chapter 26. SCC Asynchronous HDLC Mode and IrDA 26-13...
Page 726 2. In NMSI mode, conÞgure ports A and C to enable RXD, TXD, CTS, CD, and RTS. In other modes, conÞgure the TSA and its pins. 3. ConÞgure a baud rate generator to the appropriate channel clocking frequency. 26-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 727 The IrDA data link layer protocol is based on a preexisting standard asynchronous HDLC protocol. Figure 26-9 shows a serial infrared (SIR) link. MOTOROLA Chapter 26. SCC Asynchronous HDLC Mode and IrDA 26-15...
Page 728 Data Bits IR Frame 3/16 Bit Time Figure 26-10. UART and IR Frames The SIR encoding/decoding is supported only for SCC2. To activate it, set GSMR_L2[SIR] and conÞgure GSMR_L2[RDCR, TDCR] for 16x clock operation. 26-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 729 In nontransparent operation, the receiver discards additional synchronization characters (SYNCs) as they are received. In transparent mode, DLE-SYNC pairs are discarded. Normally, for proper MOTOROLA Chapter 27. SCC BISYNC Mode 27-1...
Page 730 TxBD status and control Þelds and clears the ready bit, TxBD[R]. It then starts sending the SYN1ÐSYN2 pairs or idles, according to GSMR[RTSM]. If the end of the current BD is reached and TxBD[L] is not set, only TxBD[R] is cleared. In both cases, an 27-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 731 The BCS calculations do not include SYNCs (in nontransparent mode) or DLE-SYNC pairs (in transparent mode). Note that GSMR_H[RFW] should be set for an 8-bit-wide receive FIFO for the BISYNC receiver. See Section 22.1.1, ÒGeneral SCC Mode Register (GSMR).Ó MOTOROLA Chapter 27. SCC BISYNC Mode 27-3...
Page 732 ¥ The controller can inspect data on a per-byte basis and interrupt the core each time a byte is received. ¥ The controller can be programmed so software handles the Þrst two or three bytes. The controller directly handles subsequent data without interrupting the core. 27-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 733 Initializes receive parameters in this serial channelÕs parameter RAM to reset state. Issue only when INIT RX the receiver is disabled. An resets transmit and receive parameters. PARAMETERS INIT TX AND RX PARAMETERS MOTOROLA Chapter 27. SCC BISYNC Mode 27-5...
Page 734 Ñ CHARACTER1 0x44 Ñ CHARACTER2 0x46 Ñ CHARACTER3 0x48 Ñ CHARACTER4 0x4A Ñ CHARACTER5 0x4D Ñ CHARACTER6 0x4E Ñ CHARACTER7 0x50 Ñ CHARACTER8 0x52 Ñ MASK VALUE(RCCM) Figure 27-2. Control Character Table and RCCM 27-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 735 (BSYNC[V]) is set.When using 7-bit characters with parity, the parity bit should be included in the SYNC register value. Field SYNC Reset UndeÞned Address SCC Base + 0x3E Figure 27-3. BISYNC SYNC (BSYNC) MOTOROLA Chapter 27. SCC BISYNC Mode 27-7...
Page 736 Bits Name Description Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this character is discarded. 1Ð7 Ñ All zeroes 8Ð15 SYNC SYNC character 27-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 737 CTS Lost during The channel stops sending the buffer, closes it, sets TxBD[CT], and generates a TXE interrupt if Message not masked. Transmission resumes when a command is received. RESTART TRANSMIT Transmission MOTOROLA Chapter 27. SCC BISYNC Mode 27-9...
Page 738 The PSMR is used as the BISYNC mode register, shown in Figure 27-5. PSMR[RBCS, RTR, RPM, TPM] can be modiÞed on-the-ßy. Field RBCS RTR RVD DRT Ñ Reset Addr 0xA08 (PSMR1), 0xA28 (PSMR2), 0xA48 (PSMR3), 0xA68 (PSMR4) Figure 27-5. Protocol-Specific Mode Register for BISYNC (PSMR) 27-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 739 10 Even parity. An even number must result from the calculation performed at both ends of the line. 11 High parity. If the parity bit is not high, a parity error is reported. MOTOROLA Chapter 27. SCC BISYNC Mode 27-11...
Page 740 1 Last BD in the table. After this buffer is used, the CP receives incoming data into the Þrst BD that RBASE points to. The number of BDs in this table is determined by the W bit and by overall space constraints of the dual-port RAM. 27-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 741 TxBD table. The CP uses BDs to conÞrm transmission or indicate errors so the core knows buffers have been serviced. The user conÞgures status and control bits before transmission, but the CP sets them after the buffer is sent. MOTOROLA Chapter 27. SCC BISYNC Mode 27-13...
Page 742 0 No automatic DLE transmission can occur before the data buffer. 1 The transmitter sends a DLE character before sending the buffer, which saves writing the Þrst DLE to a separate buffer in transparent mode. See TR for information on control characters. 27-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 743 GLR GLT DCC Ñ Ñ TXE RCH BSY TXB RXB Reset 0000_0000_0000_0000 Addr 0xA10 (SCCE1)/0xA14 (SCCM1); 0xA30 (SCCE2)/0xA34 (SCCM2) 0xA50 (SCCE3)/0xA54 (SCCM3); 0xA70 (SCCE4)/0xA74 (SCCM4) Figure 27-8. BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) MOTOROLA Chapter 27. SCC BISYNC Mode 27-15...
Page 744 The SCC status (SCCS) register allows real-time monitoring of RXD. The real-time status of CTS and CD are part of the port C parallel I/O. Field Ñ Ñ Reset 0000_0000 Addr 0xA17 (SCCS1), 0xA37 (SCCS2), 0xA57 (SCCS3), 0xA77 (SCCS4) Figure 27-9. SCC Status Registers (SCCS) 27-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 745 Using Table 27-15, the control character table should be set to recognize the end of the block. MOTOROLA Chapter 27. SCC BISYNC Mode 27-17...
Page 746 11. Write PRCRC with 0x0000 to comply with CRC16. 12. Write PTCRC with 0x0000 to comply with CRC16. 13. Clear PAREC for clarity. 14. Write BSYNC with 0x8033, assuming a SYNC value of 0x33. 15. Write DSR with 0x3333. 27-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 747 ENT and ENR are enabled last. After 5 bytes are sent, the TxBD is closed. The buffer is closed after 16 bytes are received. Any received data beyond 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MOTOROLA Chapter 27. SCC BISYNC Mode 27-19...
Page 748 Part V. The Communications Processor Module 27-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 749 LAN; if one is found, the station forces a jam pattern (all ones) on its frame and stops sending. Most collisions occur close to the beginning of a frame. The station waits MOTOROLA Chapter 28. SCC Ethernet Mode...
Page 750 The MPC860 Ethernet controller requires an external serial interface adaptor (SIA) and transceiver function to complete the interface to the media. This function is implemented in the Motorola MC68160 enhanced Ethernet serial transceiver (EEST). The MPC860+EEST solution provides a direct connection to the attachment unit interface (AUI) or twisted-pair (10BASE-T).
Page 751 Ñ PromiscuousÐReceives all addresses, but discards frame if reject pin asserted ¥ External content-addressable memory (CAM) support on both serial and system bus interfaces ¥ Up to eight parallel I/O pins can be sampled and appended to any frame MOTOROLA Chapter 28. SCC Ethernet Mode 28-3...
Page 752 Ethernet channel and system memory. ¥ Section 21.3, ÒNMSI ConÞguration,Ó explains how clocks are routed to SCCs through the bank of clocks. ¥ Chapter 28, ÒSCC Ethernet Mode,Ó should be read next. 28-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 753 Ethernet descriptions because it indicates when the LAN is in use. Carrier sense is deÞned as the logical OR of RENA and CLSN. Figure 28-3 shows the basic components and signals required to make an Ethernet connection between the MPC860 and EEST. MOTOROLA Chapter 28. SCC Ethernet Mode 28-5...
Page 754 If the line is busy, it waits for carrier sense to remain inactive for 6.0 ms, at which point it waits an additional 3.6 ms before it starts sending (9.6 ms after carrier sense originally became inactive). 28-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 755 Þrst received preamble bit and before detection of the start frame delimiter (SFD), the frame is also rejected. When the incoming pattern is not rejected and matches the DSR, the SFD has been detected; hunt mode is terminated and character assembly begins. MOTOROLA Chapter 28. SCC Ethernet Mode 28-7...
Page 756 Both interfaces can be used at the same time because there is no mode bit to select them, but they are described separately here for clarity. To implement an option, enable the pins needed for the implementation. Both interfaces use an MPC860 REJECT 28-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 757 FIFO. The CAM control logic must provide the information tag no later than when RENA is negated at the end of a noncollision frame and should be held stable on PB(16Ð23) until SDACK(1Ð2) indicate that the tag byte is being written to memory. MOTOROLA Chapter 28. SCC Ethernet Mode 28-9...
Page 758 CAM capturing frame data as it is written to system memory is that the data is already in parallel form when it leaves the MPC860. Figure 28-5 shows a parallel interface conÞguration. 28-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 759 32-bit bus write of the frame only if the tag byte is appended. The tag byte is appended from the sample of PB(16Ð23) if MOTOROLA Chapter 28. SCC Ethernet Mode...
Page 760 LG is set in the last BD of that frame. The controller reports frame status and length in the last BD. MFLR is defined as all in-frame bytes between the start frame delimiter and the end of the frame. 28-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 761 LAN increases overall throughput by reducing the chance of collision. PSMR[SBT] offers another way to reduce the aggressiveness of the Ethernet controller. 0x7A RFBD_PTR Hword Rx Þrst BD pointer. 0x7C TFBD_PTR Hword Tx Þrst BD pointer. MOTOROLA Chapter 28. SCC Ethernet Mode 28-13...
Page 762 DSR programming, causes 8 bytes of preamble on transmit (including the 1-byte start delimiter with the value 0xD5). 28.10 SCC Ethernet Commands Transmit and receive commands are issued to the CP command register (CPCR). Table 28-2 describes transmit commands. 28-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 763 RTS, active-low functionality. To prevent false TENA assertions to an external transceiver, conÞgure TENA as an input before issuing a CPM reset. See step 3 in Section 28.22, ÒSCC Ethernet Programming Example.Ó MOTOROLA Chapter 28. SCC Ethernet Mode 28-15...
Page 764 Receive Frame Receive Frame Ignore REJECT Ignore REJECT False Match True Receive Frame Ignore REJECT False True PROMISC Start Receive Discard Frame Discard Frame if REJECT is Asserted Figure 28-6. Ethernet Address Recognition Flowchart 28-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 765 Hash tables cannot be used to reject frames that match a set of entered addresses because unintended addresses are mapped to the same bit in the hash table. Thus, an external CAM must be used to implement this function. MOTOROLA Chapter 28. SCC Ethernet Mode 28-17...
Page 766 (PSMR[LPB, FDE] = 1). The loopback mode tells the Ethernet controller to accept received frames without signaling a collision. Setting PSMR[FDE] tells the controller that it can send while receiving without waiting for a clear line (carrier sense). 28-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 767 CRC checking cannot be disabled, but CRC errors can be ignored if checking is not required. 28.18 Ethernet Mode Register (PSMR) In Ethernet mode, the protocol-speciÞc mode register (PSMR), shown in Figure 28-7, is used as the Ethernet mode register. MOTOROLA Chapter 28. SCC Ethernet Mode 28-19...
Page 768 1 After a frame is received, the value on PB(16Ð23) is sampled and written to the end of the last buffer of the frame. This value is called a tag byte. If the frame is discarded, the tag byte is also discarded. 28-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 769 0 No SCCE[RXB] interrupt is generated after this buffer is used. 1 SCCE[RXB] or SCCE[RXF] is set when this buffer is used by the Ethernet controller. These two bits can cause interrupts if they are enabled. MOTOROLA Chapter 28. SCC Ethernet Mode 28-21...
Page 770 Data length and buffer pointer Þelds are described in Section 22.2, ÒSCC Buffer Descriptors (BDs).Ó Data length includes the total number of frame octets (including four bytes for CRC). Figure 28-9 shows an example of how RxBDs are used in receiving. 28-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 771 Data is sent to the Ethernet controller for transmission on an SCC channel by arranging it in buffers referenced by the channel TxBD table. The Ethernet controller uses TxBDs to conÞrm transmission or indicate errors so the core knows buffers have been serviced. MOTOROLA Chapter 28. SCC Ethernet Mode 28-23...
Page 772 Retransmission limit. Set when the transmitter fails (Retry Limit + 1) attempts to successfully transmit a message because of repeated collisions on the medium. The Ethernet controller writes this bit after it Þnishes attempting to send the buffer. 28-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 773 It is set immediately if no frame was in progress. GRACEFUL STOP TRANSMIT 9Ð10 Ñ Reserved, should be cleared. Set when an error occurs on the transmitter channel. Rx frame. Set when a complete frame has been received on the Ethernet channel. MOTOROLA Chapter 28. SCC Ethernet Mode 28-25...
Page 774 Figure 28-12. Ethernet Interrupt Events Example Note that the SCC status register (SCCS) cannot be used with the Ethernet protocol. The current state of the RENA and CLSN signals can be found in port C. 28-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 775 19. Write MAXD1 and MAXD2 with 0x05F0 to make the maximum DMA count 1520 bytes. 20. Clear GADDR1ÐGADDR4. The group hash table is not used. 21. Write PADDR1_H with 0x0380, PADDR1_M with 0x12E0, and PADDR1_L with 0x5634 to conÞgure the physical address 0x8003_E012_3456. MOTOROLA Chapter 28. SCC Ethernet Mode 28-27...
Page 776 TxBD is closed. Additionally, the receive buffer is closed after a frame is received. Any data received after 1520 bytes or a single frame causes a busy (out-of-buffers) condition because only one RxBD is prepared. 28-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 777 The following list summarizes the main features of the SCC in transparent mode: ¥ Flexible buffers ¥ Automatic SYNC detection on receive ¥ CRCs can be sent and received ¥ Reverse data mode MOTOROLA Chapter 29. SCC Transparent Mode 29-1...
Page 778 When the core enables the SCC receiver in transparent mode, it waits to achieve synchronization before data is received. The receiver can be synchronized to the data by a synchronization pulse or SYNC pattern. 29-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 779 If a 4-bit SYNC is selected, reception begins as soon as these four bits are received, beginning with the Þrst bit following the 4-bit SYNC. The transmitter synchronizes on the receiver pattern if GSMR_H[RSYN] = 1. MOTOROLA Chapter 29. SCC Transparent Mode 29-3...
Page 780 Diagrams for the pulse/envelope and sampling options are shown in Section 22.3.4, ÒControlling SCC Timing with RTS, CTS, and CD.Ó 29.4.1.2.1 External Synchronization Example Figure 29-1 shows synchronization using external signals. 29-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 781 An end of frame cannot be detected in the transparent data stream since there is no deÞned closing ßag in transparent mode. Therefore, if framing is needed, the user must use the CD line to alert the transparent controller of an end of frame. MOTOROLA Chapter 29. SCC Transparent Mode 29-5...
Page 782 The optional reversal of data (GSMR_H[REVD] = 1) is done just before data is stored in memory (after the CRC calculation). 29.6 SCC Transparent Parameter RAM For transparent mode, the protocol-speciÞc area of the SCC parameter RAM is mapped as in Table 29-2. 29-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 783 Initializes all transmit parameters in the serial channel parameter RAM to reset state. Issue only when INIT TX the transmitter is disabled. resets receive and transmit parameters. PARAMETERS INIT TX AND RX PARAMETERS MOTOROLA Chapter 29. SCC Transparent Mode 29-7...
Page 784 29.9 Transparent Mode and the PSMR The protocol-speciÞc mode register (PSMR) is not used by the transparent controller because all transparent mode selections are made in the GSMR. If only half of an SCC 29-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 785 0 No interrupt is generated after this buffer is used. 1 When this buffer is closed by the transparent controller, the SCCE[RXB] is set. SCCE[RXB] can cause an interrupt if it is enabled. MOTOROLA Chapter 29. SCC Transparent Mode 29-9...
Page 786 TxBD table. The CPM uses BDs to conÞrm transmission or indicate error conditions so the processor knows buffers have been serviced. Prepare status and control bits before transmission; they are set by the CPM after the buffer is sent. 29-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 787 CTS lost. Indicates the CTS was lost during frame transmission. Data length and buffer pointer Þelds are described in Section 22.2, ÒSCC Buffer Descriptors (BDs).Ó The buffer pointer can be even or odd and can reside in internal or external memory. MOTOROLA Chapter 29. SCC Transparent Mode 29-11...
Page 788 Reserved, should be cleared. Busy condition. Set when a byte or word is received and discarded due to a lack of buffers. The receiver resumes reception after it gets an command. ENTER HUNT MODE 29-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 789 The transparent controller is conÞgured with the RTS2 and CD2 pins active and CTS2 is conÞgured to be grounded internally in port C. A 16-bit CRC-CCITT is sent with each transparent frame. The FIFOs are conÞgured for fast operation. MOTOROLA Chapter 29. SCC Transparent Mode 29-13...
Page 790 Note that after 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received the Rx buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. 29-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 791 The SMCs support loopback and echo modes for testing. The SMC receiver and transmitter are double-buffered, corresponding to an effective FIFO size (latency) of two characters. Figure 30-1 shows the SMC block diagram. MOTOROLA Chapter 30. Serial Management Controllers 30-1...
Page 792 ¥ Each SMC channel fully supports the C/I and monitor channels of the GCI (IOM-2) in ISDN applications ¥ Two SMCs support the two sets of C/I and monitor channels in the SCIT channels 0 and 1 ¥ Full-duplex operation ¥ Local loopback and echo capability for testing 30-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 793 A and E bits, plus 4 C/I bits = 14 bits). It should be 15 for the SCIT channel 1 (8 data, bits, plus A and E bits, plus 6 C/I bits = 16 bits). MOTOROLA Chapter 30. Serial Management Controllers...
Page 794 00 Normal operation. 01 Local loopback mode. 10 Echo mode. 11 Reserved. SMC transmit enable. 0 SMC transmitter disabled. 1 SMC transmitter enabled. SMC receive enable. 0 SMC receiver disabled. 1 SMC receiver enabled. 30-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 795 SMC parameter RAM are discussed in the sections that follow. The SMC parameter RAM shared by the UART and transparent protocols is shown in Table 30-2. Parameter RAM for GCI protocol is described in Section 30.5.1, ÒSMC GCI Parameter RAM.Ó MOTOROLA Chapter 30. Serial Management Controllers 30-5...
Page 796 Hword Last half-word of protocol-speciÞc area. From SMC base address. SMC base = IMMR + 3E80 (SMC1), 3F80 (SMC2). Not accessed for normal operation. May hold helpful information for experienced users and for debugging. 30-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 797 Such a sequence is required if the parameters to be changed are not dynamic. If the register or bit description states that MOTOROLA Chapter 30. Serial Management Controllers 30-7...
Page 798 E is set in that RxBD. 30.2.4.4 SMC Receiver Shortcut Sequence This shorter sequence reinitializes receive parameters to their state after reset. 1. Clear SMCMR[REN]. 2. Make any changes, then issue an command. INIT RX PARAMETERS 3. Set SMCMR[REN]. 30-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 799 ¥ Other features for the SCCs as described in the GSMR However, the SMC UART frame format, shown in Figure 30-5, allows a data length of up to 14 bits. The SCC format supports only up to 8 bits. MOTOROLA Chapter 30. Serial Management Controllers 30-9...
Page 800 For example, if the receive pin is low for 257 bit times, BRKLN is 0x0101 and is accurate to within one character unit of bits. For 8 data bits, no parity, 1 stop bit, and 1 start bit, BRKLN is accurate to within 10 bits. 30-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 801 30.3.5 Data Handling Modes: Character- and Message-Oriented UART mode uses the same data structures as other modes. The structures support multibuffer operation and allows break and preamble sequences to be sent. Overrun, parity, MOTOROLA Chapter 30. Serial Management Controllers 30-11...
Page 802 30.3.7 Sending a Break A break is an all-zeros character without stop bits. It is sent by issuing a STOP TRANSMIT command. After sending any outstanding data, the SMC sends a character of consecutive 30-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 803 BRKLN. If the channel was processing a buffer when the break was received, the buffer is closed with the BR bit in the RxBD set. The RX interrupt is generated if it is enabled. MOTOROLA Chapter 30. Serial Management Controllers...
Page 804 Buffer closed on reception of idles. Set when the buffer has closed because a programmable number of consecutive idle sequences is received. The CP writes ID after received data is in the buffer. 8Ð9 Ñ Reserved, should be cleared 30-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 805 Figure 30-7 shows an example of how RxBDs are used in receiving 10 characters, an idle period, and Þve characters (one with a framing error). The example assumes that MRBLR = 8. MOTOROLA Chapter 30. Serial Management Controllers 30-15...
Page 806 Data is sent to the CPM for transmission on an SMC channel by arranging it in buffers referenced by descriptors in the channelÕs TxBD table. Using the BDs, the CP confirms transmission or indicates error conditions so that the processor knows the buffers have been serviced. 30-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 807 9-bit data, 1 start, and 1 stop, the data length Þeld should 6, because the three 9-bit data Þelds occupy three half words in memory (the 9 LSBs of each half word). MOTOROLA Chapter 30. Serial Management Controllers...
Page 808 Rx buffer. Set when a buffer is received and its associated RxBD is closed. Set no sooner than the middle of the last stop bit of the last character that is written to the receive buffer. 30-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 809 MRBLR = 0x0010. 9. Write MAX_IDL with 0x0000 in the SMC UART-speciÞc parameter RAM to disable the MAX_IDL functionality for this example. 10. Clear BRKLN and BRKEC in the SMC UART-speciÞc parameter RAM. MOTOROLA Chapter 30. Serial Management Controllers 30-19...
Page 810 However, the SMC in transparent mode provides a data character length option of 4 to 16 bits, whereas the SCCs provide 8 or 32 bits, depending on GSMR[RFW]. The SMC in transparent mode is also referred to as the SMC transparent controller. 30-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 811 SMC writes the message status bits into the BD and clears the R bit. It then starts transmitting idles. When the end of the current BD is reached and the L bit is not set, only MOTOROLA Chapter 30. Serial Management Controllers...
Page 812 (the TxBD is ready with data), data starts being send on the next falling edge of SMCLK after one character of ones is sent. If the transmit FIFO is loaded later, data starts being sent after some multiple number of all-ones characters is sent. 30-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 813 The TSA offers an alternative to using SMSYN to internally synchronize the SMC channel. This method is similar, except that the synchronization event is the Þrst time-slot for this SMC receiver/transmitter after the frame sync indication rather than the falling edge of MOTOROLA Chapter 30. Serial Management Controllers 30-23...
Page 814 SMC, SMC transmission, as well as reception, is always synchronized to the beginning of that time slot. If multiple time slots in a TDM frame are assigned to the SMC (as shown in Figure 30-12), then synchronization depends on the order of initialization. 30-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 815 Initializes transmit parameters in this serial channel to reset state. Use only if the transmitter is INIT TX disabled. The command resets transmit and receive parameters. PARAMETERS INIT TX AND RX PARAMETERS MOTOROLA Chapter 30. Serial Management Controllers 30-25...
Page 816 Figure 30-13 shows the SMC transparent RxBD format. Offset + 0 Ñ Ñ Ñ Ñ Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 30-13. SMC Transparent Receive BD (RxBD) 30-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 817 TxBD table. The CP uses BDs to conÞrm transmission or indicate error conditions so the processor knows buffers have been serviced. Figure 30-14 shows the SMC transparent TxBD format. MOTOROLA Chapter 30. Serial Management Controllers 30-27...
Page 818 CP. The data length can be even or odd, but if the number of bits in the transparent character is greater than 8, the data length should be even. For example, to transmit three transparent 8-bit characters, the data length Þeld should be initialized to 3. 30-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 819 FIFO. A two character-time delay is required to ensure that data is completely sent. Rx buffer. Set when a buffer is received (after the last character is written) on the SMC channel and its associated RxBD is closed. MOTOROLA Chapter 30. Serial Management Controllers 30-29...
Page 820 After 5 bytes are sent, the TxBD is closed; after 16 bytes are received the receive butter is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. 30-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 821 ¥ Each SMC channel can support both the C/I and monitor channels of the GCI (IOM-2) in ISDN applications ¥ Two SMCs support both sets of C/I and monitor channels in SCIT channels 0 and 1 ¥ Full-duplex operation ¥ Local loopback and echo capability for testing MOTOROLA Chapter 30. Serial Management Controllers 30-31...
Page 822 A and E control bits according to the GCI monitor channel protocol. The command resolves deadlocks when errors in the A and E bit states occur on the TIMEOUT data line. 30-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 823 The GCI monitor channel RxBD, shown in Figure 30-16, is used by the CP to report on the monitor channel receive byte. The RxBD itself receives the monitor data. Offset + 0 Ñ Data Figure 30-16. SMC GCI Monitor Channel RxBD MOTOROLA Chapter 30. Serial Management Controllers 30-33...
Page 824 EOM on the E bit after receiving an abort request. 3Ð7 Ñ Reserved, should be cleared. 8Ð15 Data Data Þeld. Contains the data to be sent by the SMC on the monitor channel. 30-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 825 C/I Data Command/indication data bits. For C/I channel 0, bits 10Ð13 hold the 4-bit data Þeld (bits 8 and 9 should be written with zeros). For C/I channel 1, bits 8Ð13 contain the 6-bit data Þeld. 14Ð15 Ñ Reserved, should be cleared. MOTOROLA Chapter 30. Serial Management Controllers 30-35...
Page 826 C/I channel buffer received. Set when the C/I receive buffer becomes full. MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer becomes empty. MRXB Monitor channel buffer received. Set when the monitor receive buffer becomes full. 30-36 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 827 SPI is disabled in the SPI mode register (SPMODE[EN] = 0), it consumes little power. Peripheral Bus SPI Mode Register Transmit_Register Receive_Register Counter Shift_Register IN_CLK Pins Interface SPIBRG BRGCLK SPISEL SPIMOSI SPIMISO SPICLK Figure 31-1. SPI Block Diagram MOTOROLA Chapter 31. Serial Peripheral Interface 31-1...
Page 828 Conversely, the master-out slave-in SPIMOSI signal is an output for master devices and an input for slave devices. The dual functionality of these signals allows the SPIs in a multimaster environment to communicate with one another using a common hardware conÞguration. 31-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 829 I/O signals to selectively enable slaves, as shown in Figure 31-2. To eliminate the multimaster error in a single-master environment, the masterÕs SPISEL input can be forced inactive by selecting port B[31] for general-purpose I/O (PBPAR[DD31] = 0). MOTOROLA Chapter 31. Serial Peripheral Interface 31-3...
Page 830 SPIMOSI between buffers. If the current TxBD[L] is set, sending stops after the current buffer is sent. In addition, the RxBD is closed after transmission stops, even if the Rx buffer is not full; therefore, Rx buffers need not be the same length as Tx buffers. 31-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 831 It also disables SPI operation and the output drivers of SPI signals. The core must clear SPMODE[EN] before the SPI is used again. After correcting the problems, clear SPIE[MME] and reenable the SPI. MOTOROLA Chapter 31. Serial Peripheral Interface 31-5...
Page 832 ¥ It is the responsibility of software to arbitrate for the SPI bus (with token passing, for example) ¥ SELOUTx signals are implemented in software with general-purpose I/O signals Figure 31-3. Multimaster Configuration 31-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 833 0 The SPI is disabled. The SPI is in a reset state and consumes minimal power. The SPI BRG is not functioning and the input clock is disabled. 1 The SPI is enabled. MOTOROLA Chapter 31. Serial Peripheral Interface 31-7...
Page 834 (SPMODE[CP] = 1). SPICLK (CI = 0) SPICLK (CI = 1) SPIMOSI (From Master) SPIMISO (From Slave) SPISEL NOTE: Q = UndeÞned Signal. Figure 31-6. SPI Transfer Format with SPMODE[CP] = 1 31-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 835 REV=1, the string is transmitted: first ghij_klmn__opqr_stuv last Example 3 with LEN=0xC (data size=13), the following data is selected: ghij_klmn__xxxr_stuv with REV=0, the string transmitted: first nmlk_jihg__vuts_r last with REV=1, the string is transmitted: first ghij_klmn__r_stuv last MOTOROLA Chapter 31. Serial Peripheral Interface 31-9...
Page 836 Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed. 31.4.3 SPI Command Register (SPCOM) The SPI command register (SPCOM), shown in Figure 31-8, is used to start SPI operation. Field Ñ Reset Addr 0xAAD Figure 31-8. SPI Command Register (SPCOM) 31-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 837 After a reset or when the end of the BD table is reached, the CPM initializes RBPTR to the RBASE value. Most applications should not modify RBPTR, but it can be updated when the receiver is disabled or when no Rx buffer is in use. MOTOROLA Chapter 31. Serial Peripheral Interface 31-11...
Page 838 1x Big-endian or true little-endian. 5Ð7 AT[1Ð3] Address type 1Ð3. Contains the user-deÞned function code value used during the SDMA channel memory access. AT0 is always driven high to identify this channel access as a DMA-type access. 31-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 839 Frame Status Data Length Tx Buffer Buffer Pointer Pointer to SPI TxBD Table RxBD Table Pointer to SPI Rx Buffer Frame Status RxBD Table Data Length Buffer Pointer Figure 31-10. SPI Memory Structure MOTOROLA Chapter 31. Serial Peripheral Interface 31-13...
Page 840 SPI is enabled. The format of an RxBD is shown in Figure 31-11. Offset + 0 Ñ Ñ Ñ Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 31-11. SPI Receive BD (RxBD) 31-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 841 Data to be sent with the SPI is sent to the CPM by arranging it in buffers referenced by TxBDs in the TxBD table. TxBD Þelds should be prepared before data is sent. The format of an TxBD is shown in Figure 31-12. MOTOROLA Chapter 31. Serial Peripheral Interface 31-15...
Page 842 Multimaster error. Indicates that this buffer is closed because SPISEL was asserted when the SPI was in master mode. An arbitration problem occurred between devices on the SPI bus. The SPI updates ME after sending the buffer. 31-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 843 14. Clear PBDAT[D15], assuming PB15 is chosen, to assert the SPI select output signal. 15. Set SPCOM[STR] to start the transfer. After 5 bytes are sent, the TxBD is closed because TxBD[L] is set. The RxBD is closed when the TxBD closes. MOTOROLA Chapter 31. Serial Peripheral Interface 31-17...
Page 844 If the master sends 16 bytes and negates SPISEL, the RxBD is closed without triggering a busy error (SPIE[BSY]). If the master sends more than 16 bytes, the RxBD is closed (full) and an SPIE[BSY] event occurs after the 17th byte is received. 31-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 845 2. Process the TxBD to reuse it and the RxBD to extract the data from it. To transmit another buffer, simply set TxBD[R], RxBD[E], and SPCOM[STR]. 3. Clear the interrupt by writing a one to CISR[SPI]. 4. Execute an rfi instruction. MOTOROLA Chapter 31. Serial Peripheral Interface 31-19...
Page 846 Part V. The Communications Processor Module 31-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 847 SCL stays low to generate bus timeouts. Peripheral Bus U Bus Rx Data Register Tx Data Register Mode Register Shift Register Shift Register Control Baud-Rate Generator Figure 32-1. I C Controller Block Diagram MOTOROLA Chapter 32. I2C Controller 32-1...
Page 848 C Master/Slave General Configuration When the I C controller is the master, the SCL clock output, taken directly from the I BRG, shifts receive data in and transmit data out through SDA. The transmitter arbitrates 32-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 849 Initialize the Þrst transmit data byte with the write request (R/W = 0) and slave address (bits 1Ð7). If the MPC860 is the slave target of the write, prepare receive buffers and BDs to await the masterÕs request. Figure 32-4 shows the timing for a master write. MOTOROLA Chapter 32. I2C Controller 32-3...
Page 850 If the MPC860 is the slave target of the read, prepare the I C transmit buffers and BDs and activate it by setting I2COM[STR]. Figure 32-5 shows the timing for a master read. 32-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 851 C controller supports this by implementing I C master arbitration in hardware. However, due to the nature of the I C bus and the implementation of the I C controller, certain software considerations must be made. MOTOROLA Chapter 32. I2C Controller 32-5...
Page 852 1 General call address is disabled. Clock Þlter. Determines if the I C input clock SCL is Þltered to prevent spikes in a noisy environment. 0 SCL is not Þltered. 1 SCL is Þltered by a digital Þlter. 32-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 853 C Baud Rate Generator Register (I2BRG) The I C baud rate generator register, shown in Figure 32-8, sets the divide ratio of the I BRG. Field Reset 1111_1111 Addr 0x868 Figure 32-8. I C Baud Rate Generator Register (I2BRG) MOTOROLA Chapter 32. I2C Controller 32-7...
Page 854 Rx buffer. Set after the last character is written to the Rx buffer and the RxBD is closed. 32.4.5 I C Command Register (I2COM) The I C command register, shown in Figure 32-10, is used to start I C transfers and to select master or slave mode. 32-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 855 Byte Rx/Tx function code. Contains the value to appear on AT[1Ð3] when the associated SDMA channel accesses memory. Also controls the byte-ordering convention for 0x05 TFCR Byte transfers. See Figure 32-11 and Table 32-7. MOTOROLA Chapter 32. I2C Controller 32-9...
Page 856 0x24 TTEMP Word Tx temp. Reserved for CP use. From I 2 base. I C base = IMMR + 0x3C80. Normally, these parameters need not be accessed. Figure 32-11 shows the RFCR/TFCR bit Þelds. 32-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 857 TxBD tables in dual-port RAM. The tables have the same basic conÞguration as for the SCCs and SMCs and form circular queues that determine the order buffers are transferred. The CPM uses BDs to conÞrm reception and transmission or to indicate error conditions so MOTOROLA Chapter 32. I2C Controller 32-11...
Page 858 C Receive Buffer Descriptor (RxBD) Using RxBDs, the CPM reports on each buffer received, closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer when the current one is full. 32-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 859 32.7.1.2 I C Transmit Buffer Descriptor (TxBD) Transmit data is arranged in buffers referenced by TxBDs in the TxBD table. The Þrst word of the TxBD, shown in Figure 32-14, contains status and control bits. MOTOROLA Chapter 32. I2C Controller 32-13...
Page 860 C controller updates UN after the buffer is sent. Collision. Indicates that transmission terminated because the transmitter was lost while arbitrating for the bus. The I C controller updates CL after the buffer is sent. 32-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 861 ¥ Transparent I/O using a single strobe ¥ Programmable handshake timing attributes ¥ Supports the Centronics receiver/transmitter interface ¥ Supports fast connection between 860s ¥ Can be controlled by the core or CP MOTOROLA Chapter 33. Parallel Interface Port 33-1...
Page 862 33.2.2 CP Control When the PIP is controlled by the CP (PIPC[HSC] = 0), any of the three handshake modes can be used. Data is prepared by the core using PIP buffer descriptors. CP-controlled 33-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 863 Tx buffer is in use. 0x22 T_CNT Hword Tx internal byte count. 0x24 TTEMP Word Tx temporary. From PIP base address. PIP base = IMMR + 0x3F80 (SMC2) MOTOROLA Chapter 33. Parallel Interface Port 33-3...
Page 864 If the core controls the transmitter, the masking function can be performed in software by reading the individual status signals for errors. When receiving, core software drives the status signals using general-purpose outputs. Field Addr PIP base + 0x05 Figure 33-3. Status Mask Register (SMASK) 33-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 865 CP initializes RBPTR to the RBASE value. Most applications should not modify RBPTR, but it can be updated if the receiver is disabled or if no Rx buffer is in use. 0x12 R_CNT Hword Rx internal byte count. MOTOROLA Chapter 33. Parallel Interface Port 33-5...
Page 866 ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ ¥ 0x3A Ñ CHARACTER8 0x3C Ñ RCCM 0x3E Ñ RCCR From PIP base address Figure 33-4. Control Character Table, RCCM, and RCCR 33-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 867 The port B registers must also be conÞgured for PIP operation. The following subsections describe the PIP registers. 33.4.1 PIP ConÞguration Register (PIPC) The PIP conÞguration (PIPC) register determines all PIP options. Figure 33-5 shows the register format. MOTOROLA Chapter 33. Parallel Interface Port 33-7...
Page 868 16 bits. (If the PIP is 8-bit, program MODL to 0b00.) 00 Port B general-purpose I/O 01 Transparent transfer modeÑcontrolled by the CP. 1x Mode of operation is controlled by MODH. Note that BUSY is not affected by MODL programming if EBSY = 1. 33-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 869 Þeld; see Section 33.5.1, ÒThe PIP Tx Buffer Descriptor (TxBD).Ó Control character received. A control character was received and stored in the received control character register (RCCR) in the PIP parameter RAM. MOTOROLA Chapter 33. Parallel Interface Port 33-9...
Page 870 256 clocks. For a 25-MHz system, the general system clock period is 40 ns. 33.4.5 The Port B Registers The PIP uses parallel I/O port B. Figure 33-8 shows the basic operation of port B. 33-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 871 However, it is never modiÞed by the CP. This value should be greater than zero. For an 8-bit PIP, this value can be odd or even; for a 16-bit PIP, it must be even. MOTOROLA Chapter 33. Parallel Interface Port...
Page 872 1 The CP does not clear R after this buffer is closed, allowing the associated buffer to be resent when the CP next accesses this BD. However, R is cleared if an error occurs during transmission. 7Ð11 Ñ Reserved and should be cleared. 33-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 873 0 No interrupt is generated after this buffer is Þlled. 1 PIPE[RXB] is set when the CP Þlls this buffer, signaling the core to process the buffer. The RXB bit causes an interrupt if not masked. MOTOROLA Chapter 33. Parallel Interface Port 33-13...
Page 874 Forces the PIP controller to close the current RxBD if it is being used and to use the next BD in the table CLOSE RXBD for subsequent data. No action is taken if the PIP controller is not receiving data. 33-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 875 Figure 33-11 shows the handshake timing of the interlocked mode. T Setup T Hold Transmitter Data Transmitter (Output Ready) Receiver (Input Ready) Figure 33-11. Interlocked Handshake Mode Timing MOTOROLA Chapter 33. Parallel Interface Port 33-15...
Page 876 (PIPC) register. When the PIP is under CP control, timing attributes are set in PTPR. Transmit and receive errors are reported through BDs. For information about supporting a Centronics interface, see Section 33.9, ÒImplementing Centronics.Ó 33-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 877 Section 33.4.4, ÒPIP Timing Parameters Register (PTPR).Ó Figure 33-14 shows how the timing parameter TPAR1 governs the setup time and TPAR2 deÞnes the pulse width of STB of a PIP transmitter using pulsed handshake mode timing. MOTOROLA Chapter 33. Parallel Interface Port 33-17...
Page 878 PIPC[TMOD]; see Table 33-6. BUSY (PB31) TPAR1 TPAR2 Figure 33-15. PIP Receiver TimingÑMode 0 BUSY (PB31) TPAR1 TPAR2 Figure 33-16. PIP Receiver TimingÑMode 1 BUSY (PB31) TPAR1 TPAR2 Figure 33-17. PIP Receiver TimingÑMode 2 33-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 879 The Centronics protocol is a parallel peripheral interface for communicating between a host computer and a printer. To implement Centronics, the PIP uses an 8-bit data bus, two handshake signals that control the data exchange, and signals that reßect the peripheral device status. MOTOROLA Chapter 33. Parallel Interface Port 33-19...
Page 880 SMASK, the PIP transmitter checks the printer status lines (SELECT, PERROR and FAULT) for Tx errors before each transfer. ConÞgure PB30, PB29, and PB28 as general-purpose inputs and connect them to SELECT, PERROR, and FAULT, respectively. 33-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 881 CP is controlling the transfer. The relevant PIPE ßags during Centronics transmission are TXE, TCH, and TXB; see Section 33.4.2, ÒPIP Event Register (PIPE).Ó For core-controlled transmissions, only the character-based TCH interrupt applies. MOTOROLA Chapter 33. Parallel Interface Port 33-21...
Page 882 BD. The relevant PIPE event bits for Centronics receiving are CCR, BSY, RCH, and RXB; see Section 33.4.2, ÒPIP Event Register (PIPE).Ó For core-controlled receiving, only the character-based RCH interrupt applies. 33-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 883 A, B, C, and D. Functions are grouped to maximize the signalsÕ usefulness to the greatest number of MPC860 applications. To understand signal assignments described in this chapter, it helps to understand each CPM peripheral. MOTOROLA Chapter 34. Parallel I/O Ports 34-1...
Page 884 PORT A12 TXD2 Ñ Ñ PA11 PORT A11 RXD3 L1TXDB UndeÞned PA10 PORT A10 TXD3 L1RXDB PORT A9 RXD4 L1TXDA UndeÞned PORT A8 TXD4 L1RXDA L1RXDA = GND PORT A7 CLK1/TIN1/L1RCLKA BRGO1 CLK1/TIN1/L1RCLKA = BRGO1 34-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 885 Setting the PAODR bits conÞgure the signals for open-drain operation. Field Ñ OD9 OD10 OD11 OD12 Ñ OD14 Ñ Reset Addr 0x954 Figure 34-1. Port A Open-Drain Register (PAODR) Available for MPC860 Rev. B and later. MOTOROLA Chapter 34. Parallel I/O Ports 34-3...
Page 886 34.2.1.3 Port A Data Direction Register (PADIR) Port A data direction register (PADIR) bits conÞgure port A signals as general-purpose inputs or outputs. If a signal is not programmed for general-purpose I/O, PADIR selects the peripheral function to be performed. 34-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 887 0 General-purpose I/O. The peripheral functions of the signal are not used. 1 Dedicated peripheral function. The signal is used by the internal module. The on-chip peripheral function to which it is dedicated can be determined by other bits. MOTOROLA Chapter 34. Parallel I/O Ports 34-5...
Page 888 See Chapter 21, ÒSerial Interface.Ó 34.2.3 Port A Functional Block Diagrams Using PA15 as an example, Figure 34-5 shows the functional block diagram for all port A signals without open-drain capability. 34-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 889 Read Path To PADAT[14] Write Path From RXD1/PA14 PADAT[14] Open Drain Output Control Latch 16-Bits PADIR 16-Bits TXD1 From SCC1 PAODR 16-Bits PAPAR Figure 34-6. Block Diagram for PA14 (True for all Open-Drain Port Signals) MOTOROLA Chapter 34. Parallel I/O Ports 34-7...
Page 890 SPIMOSI SPIMOSI = V PB28 Port B28 BRGO4 SPIMISO SPIMISO = SPIMOSI PB27 Port B27 BRGO1 I2CSDA I2CSDA = V PB26 Port B26 BRGO2 I2CSCL I2CSCL = GND PB25 Port B25 SMTXD1 Ñ Ñ 34-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 891 Ñ Reset 0000_0000_0000_0000 Ñ Addr 0xAC0 Field OD16 OD17 OD18 OD19 0D20 0D21 OD22 OD23 OD24 OD25 OD26 OD27 OD28 OD29 OD30 OD31 Reset Addr 0xAC2 Figure 34-7. Port B Open-Drain Register (PBODR) MOTOROLA Chapter 34. Parallel I/O Ports 34-9...
Page 892 34.3.1.3 Port B Data Direction Register (PBDIR) Port B data direction register (PBDIR) bits conÞgure port B signals as general-purpose inputs or outputs. If a signal is not programmed for general-purpose I/O, PBDIR selects the peripheral function to be performed. 34-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 893 Ñ Ñ Addr 0xABC Bits Field DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31 Reset Addr 0xABE Figure 34-10. Port B Pin Assignment Register (PBPAR) MOTOROLA Chapter 34. Parallel I/O Ports 34-11...
Page 894 Port C8 TGATE2 Port C7 CTS3 L1TSYNCB SDACK2 CTS3 = GND Port C6 L1RSYNCB CD3=GND Port C5 CTS4 L1TSYNCA SDACK1 CTS4 = GND Port C4 L1RSYNCA Ñ Available for MPC860 Rev. B and later. 34-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 895 Section 35.5.3, ÒCPM Interrupt Mask Register.Ó The following steps conÞgure a port C signal as a general-purpose input that generates an interrupt: 1. Write the corresponding PCPAR bit with a 0. 2. Write the corresponding PCDIR bit with a 0. MOTOROLA Chapter 34. Parallel I/O Ports 34-13...
Page 896 SCC transmission and reception with these signals. PC14 and PC15 can be programmed to assert special requests directly to the CPM by setting RCCR[EIE]; however, do not do so unless instructed by a Motorola-supplied RAM microcode package.
Page 897 1 Select the signal for general-purpose output, or select peripheral function 1. 34.4.1.3 Port C Pin Assignment Register (PCPAR) The port C pin assignment register (PCPAR) conÞgures signals as general-purpose I/O or dedicated for use with a peripheral. MOTOROLA Chapter 34. Parallel I/O Ports 34-15...
Page 898 PCINT bits. 1 PC is connected to the corresponding SCC input as well as being a general-purpose interrupt signal. 34-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 899 The port I/O signal is conÞgured as an input if the corresponding bit in the port D data direction register (PDDIR) is cleared and as an output if the bit is set. PDPAR and PDDIR MOTOROLA Chapter 34. Parallel I/O Ports...
Page 900 A write to a PDDAT bit is latched, and if conÞgured as an output, is driven onto its respective signal. PDDAT can be read or written at any time. PDDAT is not initialized and is undeÞned by reset. 34-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 901 1 The corresponding signal is an output. 34.5.1.3 Port D Pin Assignment Register (PDPAR) The port D pin assignment register (PDPAR) conÞgures signals as general-purpose I/O or dedicated for use with a peripheral. MOTOROLA Chapter 34. Parallel I/O Ports 34-19...
Page 902 0 General-purpose I/O. The peripheral functions of the signal are not used. 1 Dedicated peripheral function. The signal is used by the internal module. The on-chip peripheral function to which it is dedicated can be determined by other bits. 34-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 903 SIU, shown in the middle of Figure 35-1. All interrupts signaled by the CPIC are presented to the SIU at a single programmable priority level (0Ð7). In turn, the SIU controls which PowerPC architecture-deÞned external interrupt exception condition is reported to the PowerPC core. MOTOROLA Chapter 35. CPM Interrupt Controller 35-1...
Page 904 (CIVR). When CIVR[IACK] is set, the contents of CIVR[VN] are updated with the 5-bit vector corresponding to the sub-block with the highest current priority. CIVR[IACK] is cleared after one clock cycle. 35-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 905 CICR[SCnP], shown in Table 35-3. Table 35-1 has no explicit entry for SCCs because the entries can be mapped to any of these locations. This is programmed in the CICR (see Table 35-3). MOTOROLA Chapter 35. CPM Interrupt Controller 35-3...
Page 906 Section 35.5.3, ÒCPM Interrupt Mask Register.Ó When a masked source requests an interrupt, the corresponding CIPR bit is set but the CPIC does not signal the interrupt to the core. Masking all sources allows the implementation of a polling interrupt servicing scheme. 35-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 907 CIVR[IACK]. The CPIC passes the Þve low-order bits of the vector corresponding to the highest priority, unmasked, pending CPM interrupt in CIVR[VN]. These encodings are shown in Table 35-2. MOTOROLA Chapter 35. CPM Interrupt Controller 35-5...
Page 908 ¥ CPM interrupt mask register (CIMR)ÑCan be used to mask CPM interrupt sources. ¥ CPM interrupt in-service register (CISR)ÑAllows nesting interrupt requests within the CPM interrupt level. Note that the names and placement of bits is identical in the CIPR, CIMR, and CISR. 35-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 909 Interrupt request level. Contains the priority request level of the interrupt from the CPM that is sent to the SIU. Level 0 indicates highest priority. IRL is initialized to zero during reset. In most systems, value 0b100 is a good value to choose for IRL. MOTOROLA Chapter 35. CPM Interrupt Controller 35-7...
Page 910 CPM interrupt source is then available for the core in CIVR[VN]. However, the CIPR bit is not cleared if an event register exists for that interrupt source. Event registers exist only for interrupt sources with multiple interrupt events (for example, the SCCs). 35-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 911 TIMER1 interrupt routine could interrupt the TIMER2 interrupt handler. See Section 35.2.3, ÒNested Interrupts.Ó During this time, the user can set CISR[TIMER1] and CISR[TIMER2] simultaneously. The SCCs CISR bit positions are not affected by the relative priority between one another. MOTOROLA Chapter 35. CPM Interrupt Controller 35-9...
Page 912 1. Set CIVR[IACK]. 2. Read CIVR[VN] to determine the vector number for the interrupt handler. 3. Handle the interrupt event indicated through the port C6 signal. 4. Clear CISR[PC6]. 5. Execute the rfi instruction. 35-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 913 7. Execute the rfi instruction. If any unmasked SCCE1 bits remain (either not cleared by the software or set by the MPC860 during the execution of this handler), this interrupt source is pending again immediately after the rfi instruction. MOTOROLA Chapter 35. CPM Interrupt Controller 35-11...
Page 914 Part V. The Communications Processor Module 35-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 915 Ñ Complex (16-bit real, 16-bit imaginary) FIR loop: 4 clocks per 4 multiplies ¥ Load/store instructions with automatic post increment/decrement Ñ Post increment/decrement by 0, 1, 2, 4 Ñ Modulo addressing and modiÞer for circular buffer support MOTOROLA Chapter 36. Digital Signal Processing 36-1...
Page 916 Tx modulation DEMOD 01001 Real Complex Complex Rx demodulation LMS1 01010 Ñ Ñ Ñ EC update, equalizer update (T/2, T/3) LMS2 01011 Ñ Ñ Ñ Equalizer update (2T/3) WADD 01100 Real Ñ Real Interpolation 36-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 917 Table 36-2 describes the status and control bits. All of the library functions use the stop, wrap, and interrupt bits. The use of the remaining control bits, apart from the opcode, depends on the particular function. The parameter packets are described with the individual functions. MOTOROLA Chapter 36. Digital Signal Processing 36-3...
Page 918 Figure 36-4 shows the real number representation. Field Real Figure 36-4 Real Number Representation A complex number is represented by a pair of 16-bit componentsÑ16 bits for the imaginary component and 16 bits for the realÑas shown in Figure 36-5. 36-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 919 The FDBASE parameter deÞnes the starting address for the FD chain in system memory. FDBASE should be 16-byte aligned and should be initialized before issuing INIT Table 36-3 shows the DSPx parameter RAM memory map. MOTOROLA Chapter 36. Digital Signal Processing 36-5...
Page 920 The execution of DSP functions has a priority level within the CPM that tracks the priority level programmed for IDMA; see Section 19.3, ÒCommunicating with the Peripherals.Ó The IDMA priority (and thus the DSP priority) is programmed in the RCCR; see 36-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 921 The DSP library provides Þve basic Þnite-impulse response Þlters, each specializing in a different combination of real or complex coefÞcients, input samples, and output. The following sections describe each variety of FIR Þlter. Table 36-6 shows the parameter packet common to all FIR Þlters. MOTOROLA Chapter 36. Digital Signal Processing 36-7...
Page 922 The coefÞcient vector occupies K 16-bit entries in memory with C(0) stored in the Þrst location. The 16-bit input samples are stored in order in a circular buffer containing (M+1) bytes. The 16-bit outputs are stored consecutively in a circular buffer containing (N+1) bytes. See Table 36-7. 36-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 923 Hword 5 XYPTR Pointer to a structure composed of the input buffer pointer and the output buffer pointer Hword 6 N Output buffer_size - 1. The minimum output buffer size is 4 (2 outputs). Hword 7 Ñ Reserved MOTOROLA Chapter 36. Digital Signal Processing 36-9...
Page 924 The output buffer is a circular buffer containing (N+1) bytes. Each output is two 16-bit entries (real and imaginary components). The next output is stored in the address that follows the previous output. See Table 36-9. 36-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 925 Offset + 0xE Ñ Figure 36-12. FIR2 Function Descriptor The status and control bits (at offset 0x00) are described in Table 36-2. The FIR2 parameter packet consists of seven 16-bit entries, described in Table 36-10. MOTOROLA Chapter 36. Digital Signal Processing 36-11...
Page 926 Figure 36-14, with K complex coefÞcients, complex input samples, and real or complex output. The input data is in a circular buffer with size (M+1) and the output data is in a circular buffer with size (N+1). 36-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 927 Complex Output, FD[X]=1 Real Output, FD[X]=0 imaginary{C(0)} real{C(0)} imaginary{C(1)} imaginary {x(n-k+1)} imaginary{Y(n-k+1)} Y(n-k+1) real{C(1)} real {x(n-k+1)} real{Y(n-k+1)} Y(n-2) imaginary{C(k-1)} imaginary {x(n-2)} imaginary{Y(n-2)} Y(n-1) real{C(k-1)} real{x(n-2)} real{Y(n-2)} Y(n) imaginary{x(n-1)} imaginary{Y(n-1)} real{x(n-1)} real{Y(n-1)} imaginary{x(n)} imaginary{Y(n)} real{x(n)} real{Y(n)} MOTOROLA Chapter 36. Digital Signal Processing 36-13...
Page 928 The FIR3 with the real output is used in echo cancellation (see Figure 36-16); using the complex output implements an equalizer. Ñ IALL INDEX Ñ OPCODE Offset + 0 00011 Offset + 2 I=3 (Three Iterations) Figure 36-16. FIR3 Echo Cancellation Example 36-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 929 Table 36-13. FIR5 Coefficient, Input, and Output Buffers CoefÞcients Input Samples Complex Output, FD[X]=1 Real Output, FD[X]=0 imaginary{C(0)} real{C(0)} imaginary{C(1)} imaginary {x(n-k+1)} imaginary{Y(n-k+1)} Y(n-k+1) real{C(1)} real {x(n-k+1)} real{Y(n-k+1)} Y(n-2) imaginary{C(k-1)} imaginary {x(n-2)} imaginary{Y(n-2)} Y(n-1) MOTOROLA Chapter 36. Digital Signal Processing 36-15...
Page 930 FD[X] = 0 is 4 (2 outputs). Hword 7 Ñ Reserved 36.11.4.3 FIR5 Applications The FIR5 is used for fractionally spaced equalizers. The partial FD shown in Figure 36-19 can be used to implement a fractionally spaced equalizer. 36-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 931 The output buffer is a circular buffer that contains (N+1) bytes and the next output is stored in the address that follows the previous output. See Table 36-15. MOTOROLA Chapter 36. Digital Signal Processing 36-17...
Page 932 Table 36-16. FIR6 Parameter Packet Address Name Description Hword 1 Number_of_iterations Hword 2 Number_of_taps - 1. The number of taps should be a multiple of 2. Hword 3 CBASE Filter coefÞcient vector base address 36-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 933 (M+1) bytes. The next sample is stored in the address that follows the previous one. The output buffer is a circular buffer that contains (N+1) bytes and the next output is stored in the address that follows the previous one. See Table 36-17. MOTOROLA Chapter 36. Digital Signal Processing 36-19...
Page 934 Pointer to a structure composed of the input buffer pointer and the output buffer pointer Hword 6 Output buffer_size - 1. The minimum output buffer size is 4 (2 outputs). Hword 7 Ñ Reserved 36-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 935 Input Samples Complex Output, FD[X]=1 Real Output, FD[X]=0 sin q cos q sin q imaginary{x(n-k+1)} imaginary{Y(n-k+1)} real{Y(n-k+1)} cos q real{x(n-k+1)} real{Y(n-k+1)} real{Y(n-2)} sin q imaginary{x(n-2)} imaginary{Y(n-2)} real{Y(n-1) cos q real{x(n-2)} real{Y(n-2)} real{Y(n)} imaginary{x(n-1)} imaginary{Y(n-1)} MOTOROLA Chapter 36. Digital Signal Processing 36-21...
Page 936 FD[X] = 0 is 4 (2 samples). Hword 7 Ñ Reserved 36.13.3 MOD Applications The MOD function is used in modulation. The partial FD shown in Figure 36-26 can be used to implement a modulator. 36-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 937 The AGC constant is in the range -1£ AGC£1. See Table 36-21. Table 36-21. DEMOD Modulation Table, Input, and Output Buffers Modulation Table Input Samples Output (Complex) sin q cos q sin q x(n-k+1) imaginary{Y(n-k+1)} cos q real{Y(n-k+1)} x(n-2) sin q x(n-1) imaginary{Y(n-2)} MOTOROLA Chapter 36. Digital Signal Processing 36-23...
Page 938 Pointer to a structure composed of the input buffer pointer and the output buffer pointer Hword 6 Output buffer_size - 1. The minimum output buffer size is 8 (2 outputs). Hword 7 Ñ Reserved 36-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 939 Table 36-23. LMS1 Coefficients and Input Buffers CoefÞcients Input Samples imaginary{C(0)} real{C(0)} imaginary{C(1)} imaginary{X(n-k+1)} real{C(1)} real{X(n-k+1)} imaginary{C(k-1)} imaginary{X(n-2)} real{C(k-1)} real{X(n-2)} imaginary{X(n-1)} real{X(n-1)} imaginary{X(n)} real{X(n)} MOTOROLA Chapter 36. Digital Signal Processing 36-25...
Page 940 The coefÞcients and input samples are complex numbers, but the scalar is a real or complex number. C n 1 C n i E ´ X n i Ð Figure 36-32. LMS2 Function 36-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 941 Ñ 01011 Offset + 0x2 Ñ Offset + 0x4 Offset + 0x6 CBASE Offset + 0x8 Offset + 0xA XPTR Offset + 0xC EPTR Offset + 0xE Ñ Figure 36-33. LMS2 Function Descriptor MOTOROLA Chapter 36. Digital Signal Processing 36-27...
Page 942 16-bit entry and the next sample is stored in the address that follows the previous sample. The output buffer is a circular buffer that contains (N+1) bytes. Each output is 16 bits and the newest output is stored in the address that follows the previous one. 36-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 943 Hword 5 XYPTR Pointer to a structure composed of X input buffer pointer, the output buffer pointer, and the X input buffer pointer. Hword 6 Output buffer_size - 1 Hword 7 Ñ Reserved MOTOROLA Chapter 36. Digital Signal Processing 36-29...
Page 944 1.14 million instructions per second. void tx_filter () S16 *coefr S16 *samplr, *sampli S16 *coefend; S32 filtoutr, filtouti; U8 subcount, sampleindex; extern S16 mult(S16 p1, S16 p2); /* in-line invocation */ coefr=txfiltcoef_str; coefend=txfiltcoef_end; samplr=&txfiltdly[REAL][txfiltptr]; 36-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 945 The performance load on the core from executing the Þlter software is negligible. The performance load on the CPM is based on the functions called, the number of clocks required to perform those functions and the transmission symbol rate. Using the CPM, this MOTOROLA Chapter 36. Digital Signal Processing 36-31...
Page 946 /* interrupt on completion */ /* define for function opcodes */ #define FIR_2 0x0102 /* FIR2 filter */ #define MOD 0x0008 /* Modulation function opcode */ /* Initialize a static fd chain of 2 functions */ 36-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 947 = number of taps. As seen in Table 36-30, the CPM loading from DSP applications depends on which functions are called and their parameters. The frequency with which the functions are called also affects CPM loading. MOTOROLA Chapter 36. Digital Signal Processing 36-33...
Page 948 Part V. The Communications Processor Module 36-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 949 PowerPC architecture. MPC8xx Documentation Supporting documentation for the MPC860 can be accessed through the world-wide web at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical speciÞcations, reference materials, and detailed applications notes. MOTOROLA Part VI. Debug and Test...
Page 950 Built-in self test Communication processor module IEEE Institute of Electrical and Electronics Engineers JTAG Joint Test Action Group Least-signiÞcant byte Least-signiÞcant bit Load/store unit Most-signiÞcant byte Most-signiÞcant bit Receive Special-purpose register Test access port Transmit VI-ii MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 951 Because of this, program trace is deciphered by monitoring fetched code and instruction queue ßushes, and MOTOROLA Chapter 37. System Development and Debugging 37-1...
Page 952 (I-cache and internal memory). In VSYNC state, performance degrades because of the additional external bus cycles. However, this degradation is very small. 37-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 953 11 Used for debug mode indication. Should be ignored by the program trace external hardware. See Section 37.3.1, ÒDebug Mode Operation.Ó Table 37-3 describes possible instruction queue ßushes as they are identiÞed by VF encodings. MOTOROLA Chapter 37. System Development and Debugging 37-3...
Page 954 0b111 should be interpreted as an instruction fetch type encoding, as described by Table 37-4. This is easily monitored since the only case where this can happen is when VF = 111 and the maximum number of possible queue ßushes is Þve. 37-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 955 Section 37.1.1, ÒProgram Trace Functional Description.Ó After exiting VSYNC state, the trace buffer holds the trace of the program executed before the pertinent event occurred. MOTOROLA Chapter 37. System Development and Debugging 37-5...
Page 956 37.1.5.3 Detecting the Trace Window Start Address When using back trace, latching of VF, VFLS, and the address of the cycles marked program trace cycle should all start immediately after the negation of reset. The start 37-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 957 External hardware can be added to eliminate all canceled instructions and report only on taken/not taken branches, indirect ßow change, and the number of sequential instructions after the last ßow change. MOTOROLA Chapter 37. System Development and Debugging 37-7...
Page 958 MSR[RI]. Although they count watchpoints, counters are part of the internal breakpoint logic and are not decremented when the core operates in masked mode and MSR[RI] = 0. Figure 37-1 shows the coreÕs watchpoint and breakpoint support. 37-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 959 ¥ L-data comparators can be programmed to treat integers as signed or unsigned. ¥ Combined comparator pairs to detect in and out of range conditions, including either signed or unsigned values on the L-data. MOTOROLA Chapter 37. System Development and Debugging 37-9...
Page 960 37.2.2 Internal Watchpoints and Breakpoints Logic Internal breakpoint and watchpoint support is based on the following: ¥ Eight comparators comparing information on instruction and load/store cycles ¥ Two counters ¥ Two AND-OR logic structures 37-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 961 Each of the four instruction address comparators (AÐD), shown in Figure 37-2, is 30 bits long and generates two output signalsÑequal and less than. These signals generate one of four eventsÑequal, not equal, greater than, or less than. The instruction watchpoints and MOTOROLA Chapter 37. System Development and Debugging 37-11...
Page 962 As shown in Figure 37-3, each comparator generates two output signalsÑequal and less than. These signals generate one of four events from each comparatorÑequal, not equal, greater than, or less than. See Section 37.2.4.2, ÒByte and Half Word Working Modes.Ó 37-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 963 The rest are negated. If the executed cycle has a smaller size than the compare size (a byte access when the compare size is word or half-word), no match indication is asserted. The match indication signals generate four load/store data events as shown in Table 37-7. MOTOROLA Chapter 37. System Development and Debugging 37-13...
Page 964 When programmed to count load/store watchpoints, the last instruction that decrements the counter to zero is treated like any other 37-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 965 L-address value will be of the word (byte 0). Therefore, the core masks the two lsbs of the L-address comparators for word accesses and the lsb for half-word accesses. Address range is supported only when aligned according to access size. MOTOROLA Chapter 37. System Development and Debugging 37-15...
Page 966 One L-data comparator = 0x4E204E20 and program for greater than. One L-data comparator = 0x9C409C40 and program for less than. Both byte masks = 0x0. Both L-data comparators program to half-word or word mode. 37-16 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 967 This is used for Ògo from xÓ. IFM is set by software and cleared by hardware; after the Þrst instruction breakpoint, the match is ignored. Load/store breakpoints and all counter-generated breakpoints (instruction and load/store) are unaffected by this mode. MOTOROLA Chapter 37. System Development and Debugging 37-17...
Page 968 Ñ Enable the address or data event in LCTRL2[LWxLADC] or LCTRL2[LWxLDDC] 5. Disable instruction events affecting load/store watchpointsÑClear LWxIADC (LWxIA is a donÕt care). 6. Enable the watchpoint in LCTRL2[LWxEN]. 7. Enable a trap on every watchpoint or every N watchpoints. 37-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 969 In debug mode, the rÞ instruction returns the machine to its regular work mode. Figure 37-5 shows the relationship between debug mode logic and the rest of the core. MOTOROLA Chapter 37. System Development and Debugging 37-19...
Page 970 ¥ Maskable breakpoint is used to assert the maskable external breakpoint. ¥ VSYNC control code is used to assert and negate VSYNC operation. In debug mode, the development port also controls the debug mode features of the core. See Section 37.3.2, ÒDevelopment Port Communication.Ó 37-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 971 ¥ After entry into debug mode, program execution continues from the where debug mode was entered. ¥ All instructions are fetched from the development port, while load/store accesses are performed on the real system memory in debug. MOTOROLA Chapter 37. System Development and Debugging 37-21...
Page 972 ÒSoftware Monitor Debugger Support.Ó All development support registers accessible only when the core is in debug mode; therefore, the development system has full control of the coreÕs development support features. For more information, see Table 37-15. If debug 37-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 973 ¥ Decrementer interrupt, recognized when MSR[EE] = 1. ¥ System call exception. ¥ Trace, asserted when in single or branch trace mode, as described in Section 7.1.2.10, ÒTrace Exception (0x00D00).Ó ¥ Implementation-dependent software emulation exception. MOTOROLA Chapter 37. System Development and Debugging 37-23...
Page 974 Core Response to Machine Check ICR Value Enable Interrupt Enter the checkstop state 0x20000000 Branch to machine check interrupt 0x10000000 Enter checkstop state 0x20000000 Enter debug mode 0x20000000 Branch to machine check interrupt 0x10000000 Enter debug mode 0x10000000 37-24 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 975 Figure 37-5 shows the relationship of the development support logic to the rest of the core. For clarity, the development port support logic is shown as a separate block. MOTOROLA Chapter 37. System Development and Debugging 37-25...
Page 976 This indication can be used to halt any off-chip device while in debug mode and is a handshake between the debug tool and port. In addition to FRZ, the freeze state is indicated by the value 0b11 on VFLS[0Ð1], shown in Figure 37-8. 37-26 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 977 The trap enable bits are reßected in ICTRL and LCTRL2. Section 37.5.1.1, ÒComparator AÐH Value Registers (CMPAÐCMPH),Ó describes support registers. MOTOROLA Chapter 37. System Development and Debugging 37-27...
Page 978 7 or 32 input data bits. Debug port drives the ÒreadyÓ bit onto DSDO when ready for a new transmission. NOTE: DSCK and DSDI transitions are not required to be synchronous with CLKOUT. Figure 37-9. Asynchronous Clocked Serial Communications 37-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 979 SRESET. If it is latched low, asynchronous clocked mode is enabled. If it is latched high, then synchronous self-clocked mode is enabled. The timing diagram in Figure 37-11 shows the clock mode selection after reset. MOTOROLA Chapter 37. System Development and Debugging 37-29...
Page 980 The development port shift register is 35 bits wide, but trap enable mode transmissions only use 10 of the 35 bits as the followingÑthe start/ready bit, a mode/status bit, a control/status bit, and the 7 least-signiÞcant data bits. 37-30 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 981 In trap enable mode there is no data from the core out of the development port. Data out of the development port in the trap enable mode is shown in Table 37-12. MOTOROLA Chapter 37. System Development and Debugging 37-31...
Page 982 32-bit data Þeld. Table 37-13 shows the encoding of data shifted into the development port shift register through DSDI. Data values in the last two functions other than those speciÞed are reserved. 37-32 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 983 Also, an interrupt recognized when there is valid data is not related to the execution of an instruction, therefore, a valid data status is output and the interrupt status is saved for the next transmission. MOTOROLA Chapter 37. System Development and Debugging 37-33...
Page 984 In this example, RX = r31 and RY = r30. The sequence is repeated until the end download procedure command is issued to the debug port. GPR31 temporarily stores the data value. Before issuing the start download procedure command, the value of the Þrst memory block 37-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 985 Only before the last rÞ instruction does software need to clear the ICR. The above mechanism allows software to accurately control the assertion and negation of the freeze line. MOTOROLA Chapter 37. System Development and Debugging 37-35...
Page 986 Fetch sync on write 00100 10101 Fetch sync on write 10011 10110 DPDR Read and Write The development support/debug registers are protected as described in Table 37-15. Note the special behavior of the ICR and DPDR. 37-36 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 987 Table 37-16 describes CMPAÐCMPD Þelds. Table 37-16. CMPAÐCMPD Field Descriptions Bits Name Description 0Ð29 CMPV Address bits to be compared. 30Ð31 Ñ Reserved. Figure 37-15 shows CMPEÐCMPF, which are used for load/store address bus comparisons. MOTOROLA Chapter 37. System Development and Debugging 37-37...
Page 988 The breakpoint address register (BAR), shown in Figure 37-17, is used to hold the address of the load/store cycle that generated a breakpoint. É Field BARV Reset UndeÞned Figure 37-17. Breakpoint Address Register (BAR) 37-38 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 989 10 Match from comparator C 11 Match from comparators (C & D) 18Ð19 Instruction fourth watchpoint programming. 0x Not active (reset value) 10 Match from comparator D 11 Match from comparators (C | D) MOTOROLA Chapter 37. System Development and Debugging 37-39...
Page 990 The load/store support comparators control register (LCTRL1), shown in Figure 37-19, is used to conÞgure load/store address breakpoint operations. Field CRWE CRWF Field SUSG SUSH CGBMSK CHBMSK Ñ Reset 0000_0000_0000_0000 Figure 37-19. Load/Store Support Comparators Control Register (LCTRL1) 37-40 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 991 LW0LA LW0LADC LW0LD LW0LDDC LW1EN LW1IA LW1IADC LW1LA 17 18 23 24 Field LW1LADC LW1LD LW1LDDC BRKNOMSK Ñ DLW0EN DLW1EN SLW0EN SLW1EN Reset 0000_0000_0000_0000 Figure 37-20. Load/Store Support AND-OR Control Register (LCTRL2) MOTOROLA Chapter 37. System Development and Debugging 37-41...
Page 992 1 Care 14Ð1 LW1LA Second load/store watchpoint load/store address events selection. 00 Match from comparator E 01 Match from comparator F 10 Match from comparators (E & F) 11 Match from comparators (E | F) 37-42 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 993 LWxLD. All three conditions must be detected to assert a watchpoint. 37.5.1.6 Breakpoint Counter Value and Control Registers (COUNTA/COUNTB) The breakpoint counter value and control registers (COUNTA/COUNTB), shown in Figure 37-21, can be programmed with the preset count value and counter source. MOTOROLA Chapter 37. System Development and Debugging 37-43...
Page 994 Field Ñ RST CHSTP Ñ EXTI ALI PRI FPUVI DECI Ñ SYSI Ñ Field Ñ SEI ITLBMS DTLBMS ITLBER DTLBER Ñ LBRK IBRK EBRK DPI Reset 0000_0000_0000_0000 Figure 37-22. Interrupt Cause Register (ICR) 37-44 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 995 DTLBE Implementation-speciÞc DTLB error. Set as a result of an DTLB error. results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. MOTOROLA Chapter 37. System Development and Debugging 37-45...
Page 996 0 Debug mode entry is disabled 1 Debug mode entry is enabled (reset value) MCIE Machine check interrupt enable bit 0 Debug mode entry is disabled (reset value) 1 Debug mode entry is enabled 37-46 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 997 It is used for data interchange between the core and the development system. The DPDR is accessed by using mtspr and mfspr and implemented using a special bus cycle on the internal bus. See Section 37.3.2.2.1, ÒDevelopment Port Shift Register.Ó MOTOROLA Chapter 37. System Development and Debugging 37-47...
Page 998 Part VI. Debug and Test 37-48 MPC860 PowerQUICC UserÕs Manual MOTOROLA...
Page 999 TDO changes on the falling edge of TCK. ¥ TRST An asynchronous reset with an internal pull-up resistor that provides Ñ initialization of the TAP controller and other logic required by the standard. MOTOROLA Chapter 38. IEEE 1149.1 Test Access Port 38-1...
Page 1000 TMS signal. It is a synchronous state machine that controls the operation of the JTAG logic. The value shown adjacent to each bubble represents the value of the TMS signal sampled on the rising edge of TCK. Figure 38-2 shows the MPC860 TAP controller state machine. 38-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA...

Motorola MPC860 PowerQUICC User Manual

Chapter 1 MPC860 Overview

Chapter 2 Memory Map

Chapter 3 Hardware Interface Overview

Chapter 4 The Powerpc Core

Chapter 5 Powerpc Core Register Set

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