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Interrupts
NOTE
When the GPT channel 3 registers contain 0xFFFF and TCRE
is set, TOF does not get set even though the GPT counter
registers go from 0xFFFF to 0x0000.
When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any
access to the GPT counter registers clears GPT flag register 2.
When TOF is set, it does not inhibit future overflow events.
MOTOROLA
Chapter 20. General Purpose Timer Modules (GPTA and GPTB)
20-23
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