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SDRAM Controller Operation
15.2.1 DRAM Controller Signals
Table 15-2 describes the behavior of DRAM signals in synchronous mode.
Signal
SRAS
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM.
SRAS should be connected to the corresponding SDRAM SRAS.
SCAS
Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM.
SCAS should be connected to the corresponding SDRAM SCAS.
DRAMW
DRAM read/write. Asserted for write operations and negated for read operations.
SDRAM_CS[1:0] Row address strobe. Select each memory block of SDRAMs connected to the MCF5282. One SDRAM_CS signal
selects one SDRAM block and connects to the corresponding CS signals.
SCKE
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and
disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down mode in which operations
are suspended or capable of entering self-refresh mode. SCKE functionality is controlled by DCR[COC]. For designs
using external multiplexing, setting COC allows SCKE to provide command-bit functionality.
BS[3:0]
Column address strobe. BS[3:0] function as byte enables to the SDRAMs. They connect to the BS signals (or mask
qualifiers) of the SDRAMs.
15.2.2 Memory Map for SDRAMC Registers
The DRAM controller registers memory map is shown in Table 15-3.
IPSBAR
[31:24]
Offset
0x040
DRAM control register (DCR) [p. 15-5]
0x044
0x048
0x04C
0x050
0x054
15-4
Table 15-2. Synchronous DRAM Signal Connections
Table 15-3. DRAM Controller Registers
[23:16]
DRAM address and control register 0 (DACR0) [p. 15-6]
DRAM mask register block 0 (DMR0) [p. 15-8]
DRAM address and control register 1 (DACR1) [p. 15-6]
DRAM mask register block 1 (DMR1) [p. 15-8]
MCF5282 User's Manual
Description
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MOTOROLA
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