Interrupt Controller Base Addresses; Memory Map; Interrupt Controller Memory Map - Motorola ColdFire MCF5281 User Manual

10.2 Memory Map

The register programming model for the interrupt controllers is memory-mapped to a
256-byte space. In the following discussion, there are a number of program-visible registers
greater than 32 bits in size. For these control fields, the physical register is partitioned into
two 32-bit values: a register "high" (the upper longword) and a register "low" (the lower
longword). The nomenclature <reg_name>H and <reg_name>L is used to reference these
values.
The registers and their locations are defined in Table 10-3. The offsets listed start from the
base address for each interrupt controller. The base addresses for the interrupt controllers
are listed below:
Table 10-2. Interrupt Controller Base Addresses
Interrupt Controller Number
Global IACK Registers Space
1
This address space only contains the SWIACK and L1ACK-L7IACK registers. See Section 10.3.7, "Software
and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)" for more information
Module Offset
0x00
0x04
0x08
0x0c
0x10
0x14
0x18
0x1c - 0x3c
0x40
0x44
0x48
0x4c
0x50
0x54
0x58
0x5C
MOTOROLA
INTC0
INTC1
1
Table 10-3. Interrupt Controller Memory Map
Bits[31:24] Bits[23:16]
Interrupt Pending Register High (IPRH), [63:32]
Interrupt Pending Register Low (IPRL), [31:1]
Interrupt Mask Register High (IMRH), [63:32]
Interrupt Mask Register Low (IMRL), [31:0]
Interrupt Force Register High (INTFRCH), [63:32]
Interrupt Force Register Low (INTFRCL), [31:1]
IRLR[7:1] IACKLPR[7:0]
Reserved
ICR04
ICR08
ICR12
ICR16
ICR20
ICR24
ICR28
Chapter 10. Interrupt Controller Modules
Base Address
IPSBAR + 0xC00
IPSBAR + 0xD00
IPSBAR + 0xF00
Bits[15:8]
Reserved
ICR01 ICR02
ICR05 ICR06
ICR09 ICR10
ICR13 ICR14
ICR17 ICR18
ICR21 ICR22
ICR25 ICR26
ICR29 ICR30
Memory Map
Bits[7:0]
Reserved
ICR03
ICR07
ICR11
ICR15
ICR19
ICR23
ICR27
ICR31
10-5