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Chapter 27
Queued Analog-to-Digital Converter (QADC)
The queued analog-to-digital converter (QADC) is a 10-bit, unipolar, successive
approximation converter. Up to eight analog input channels can be supported using internal
multiplexing. A maximum of 18 input channels can be supported in the expanded,
externally multiplexed mode.
The QADC consists of an analog front-end and a digital control subsystem. The analog
section includes input pins, an analog multiplexer, and sample and hold analog circuits.
The digital control section contains queue control logic to sequence the conversion process
and interrupt generation logic. Also included are the periodic/interval timer, control and
status registers, the conversion command word (CCW) table, random-access memory
(RAM), and the result table RAM.
The bus interface unit (BIU) provides access to registers that configure the QADC, control
the analog-to-digital converter and queue mechanism, and present formatted conversion
results.
27.1 Features
Features of the QADC module include:
• Internal sample and hold
• Up to eight analog input channels using internal multiplexing
• Up to four external analog multiplexers directly supported
• Up to 18 total input channels with internal and external multiplexing
• Programmable input sample time for various source impedances
• Two conversion command word (CCW) queues with a total of 64 entries for setting
conversion parameters of each A/D conversion
• Subqueues possible using pause mechanism
• Queue complete and pause interrupts available on both queues
• Queue pointers indicating current location for each queue
• Automated queue modes initiated by:
MOTOROLA
Chapter 27. Queued Analog-to-Digital Converter (QADC)
27-1
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