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9.3.3 Reset Sequence
A reset sequence depends on the operational state of the chip when the reset occurs.
• An internally provided circuit detects the power-on condition and provides an
immediate reset to the "eight cycle stretcher" input, ensuring that all the on-chip
circuits are properly initialized (i.e., all the peripherals and the CPU core are in
their reset state). The CLKOUT pin is disabled.
• The reset circuit propagates the negation of the reset source and, following the
stretcher delay of eight LOW_REFCLK cycles, negates the internal CPU core
reset.
• After an initial power-up interval, the power-up-reset circuitry is not activated;
thus an external reset trigger is first qualified for four LOW_REFCLK clock
cycles before being propagated into the internal reset circuitry. It then functions
with the same sequence as the power-up sequence.
• A watchdog reset is propagated immediately to the internal reset circuitry.
The state of the external MOD pin is latched four LOW_REFCLK cycles before the
RSTOUT pin is negated, and this state is used to control the first memory access for
the initial program counter value. The memory access is from either the internal ROM
or external memory connected to CS0.
9.3.4 Reset Source/Chip Configuration Register (RSCR)
This status and control register gives the state of the reset sources and serves to
control the CLKOUT pin. Writes to this register clear any previously set status bits.
Access this register with 32-bit loads and stores only.
RSCR — Reset Source/Chip Configuration Register
31
30
29
28
R
0
0
0
0
W
RESET:
15
14
13
12
R
0
0
0
0
W
RESET:
* = See bit description
CKOS — CLKOUT Source
This bit controls the clock source for the CLKOUT pin. Modify this pin only when the
clock output has been disabled. This bit is cleared by POR, a qualified assertion of
the RSTIN pin, or a qualified assertion of the LVRSTIN pin.
0 = CLKOUT source is HI_REFCLK
1 = CLKOUT source is LOW_REFCLK
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
27
26
25
24
0
0
0
0
11
10
9
8
0
0
CKOS CKOE
0*
0*
Figure 9-2 Reset Source Register
TIMER/RESET MODULE
For More Information On This Product,
Go to: www.freescale.com
23
22
21
20
0
0
0
0
7
6
5
4
LVRST
0
0
0
0
10001000
19
18
17
16
0
0
0
0
3
2
1
0
RST
POR
WDR
IN
*
*
*
0*
MOTOROLA
9-3
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