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Bit(s)
Name
7–2
—
1
PAOVF
0
PAIF
When the fast flag clear all enable bit, GPTSCR1[TFFCA], is
set, any access to the pulse accumulator counter registers clears
all the flags in GPTPAFLG.
20.5.17 Pulse Accumulator Counter Register (GPTPACNT)
15
Field
Reset
R/W
Address
Figure 20-19. Pulse Accumulator Counter Register (GPTPACNT)
Bit(s)
Name
15–0
PACNT
MOTOROLA
Chapter 20. General Purpose Timer Modules (GPTA and GPTB)
Table 20-19. GPTPAFLG Field Descriptions
Reserved, should be cleared.
Pulse accumulator overflow flag. Set when the 16-bit pulse accumulator rolls over from
0xFFFF to 0x0000. If the GPTPACTL[PAOVI] bit is also set, PAOVF generates an
interrupt request. Clear PAOVF by writing a 1 to it. This bit is read anytime, write
anytime. (Writing 1 clears the flag; writing 0 has no effect.)
1 Pulse accumulator overflow
0 No pulse accumulator overflow
Pulse accumulator input flag. Set when the selected edge is detected at the PAI pin.
In event counter mode, the event edge sets PAIF. In gated time accumulation mode,
the trailing edge of the gate signal at the PAI pin sets PAIF. If the PAI bit in GPTPACTL
is also set, PAIF generates an interrupt request. Clear PAIF by writing a 1 to it.
1 Active PAI input
0 No active PAI input
NOTE
0000_0000_0000_0000
IPSBAR + 0x1A_001A, 0x1B_001B
Table 20-20. GPTPACR Field Descriptions
Contains the number of active input edges on the PAI pin since the last reset.
Note: Reading the pulse accumulator counter registers immediately after an active
edge on the PAI pin may miss the last count since the input first has to be synchronized
with the bus clock.
To ensure coherent reading of the PA counter, such that the counter does not
increment between back-to-back 8-bit reads, it is recommended that only word (16-bit)
accesses be used. These bits are read anytime, write anytime.
Description
PACNT
R/W
Description
Memory Map and Registers
0
20-15
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