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Functional Description
28.5.1.2 External Reset
Asserting the external RSTI for at least four rising CLKOUT edges causes the external reset
request to be recognized and latched. The bus monitor is enabled and the current bus cycle
is completed. The reset controller asserts RSTO for approximately 512 cycles after RSTI is
negated and the PLL has acquired lock. The part then exits reset and begins operation.
In low-power stop mode, the system clocks are stopped. Asserting the external RSTI in stop
mode causes an external reset to be recognized.
28.5.1.3 Watchdog Timer Reset
A watchdog timer timeout causes timer reset request to be recognized and latched. The bus
monitor is enabled and the current bus cycle is completed. If the RSTI is negated and the
PLL has acquired lock, the reset controller asserts RSTO for approximately 512 cycles.
Then the part exits reset and begins operation.
28.5.1.4 Loss-of-Clock Reset
This reset condition occurs in PLL clock mode when the LOCRE bit in the SYNCR is set
and either the PLL reference or the PLL itself fails. The reset controller asserts RSTO for
approximately 512 cycles after the PLL has acquired lock. The part then exits reset and
begins operation.
28.5.1.5 Loss-of-Lock Reset
This reset condition occurs in PLL clock mode when the LOLRE bit in the SYNCR is set
and the PLL loses lock. The reset controller asserts RSTO for approximately 512 cycles
after the PLL has acquired lock. The part then exits reset and resumes operation.
28.5.1.6 Software Reset
A software reset occurs when the SOFTRST bit is set. If the RSTI is negated and the PLL
has acquired lock, the reset controller asserts RSTO for approximately 512 cycles. Then the
part exits reset and resumes operation.
28.5.1.7 LVD Reset
The LVD reset will occur when the supply input voltage, V
drops below V
DD,
LVD
(minimum).
MOTOROLA
Chapter 28. Reset Controller Module
28-7
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