Gptn3; Syncn; Memory Map And Registers; Gpt Modules Memory Map - Motorola ColdFire MCF5281 User Manual

Memory Map and Registers

20.4.2 GPTn3

The GPTn3 pin is for channel 3 input capture and output compare functions or for the pulse
accumulator input. This pin is available for general-purpose I/O when not configured for
timer functions.

20.4.3 SYNCn

The SYNCn pin is for synchronization of the timer counter. It can be used to synchronize
the counter with externally-timed or clocked events. A high signal on this pin clears the
counter.
20.5 Memory Map and Registers
See Table 20-3 for a memory map of the two GPT modules. GPTA has a base address of
IPSBAR + 0x1A_0000. GPTB has a base address of IPSBAR + 0x1B_0000.
Reading reserved or unimplemented locations returns zeroes.
Writing to reserved or unimplemented locations has no effect.
IPSBAR Offset
GPTA GPTB
0x1A_0000 0x1B_0000
0x1A_0001 0x1B_0001
0x1A_0002 0x1B_0002
0x1A_0003 0x1B_0003
0x1A_0004 0x1B_0004
0x1A_0006 0x1B_0006
0x1A_0007 0x1B_0007
0x1A_0008 0x1B_0008
0x1A_0009 0x1B_0009
0x1A_000A 0x1B_000a
0x1A_000B 0x1B_000b
0x1A_000C 0x1B_000c
0x1A_000D 0x1B_000d
0x1A_000E 0x1B_000e
0x1A_000F 0x1B_000f
20-4
NOTE
Table 20-3. GPT Modules Memory Map
GPT IC/OC Select Register (GPTIOS)
GPT Compare Force Register (GPTCFORC)
GPT Output Compare 3 Mask Register (GPTOC3M)
GPT Output Compare 3 Data Register (GPTOC3D)
GPT Counter Register (GPTCNT)
GPT System Control Register 1 (GPTSCR1)
GPT Toggle-on-Overflow Register (GPTTOV)
GPT Control Register 1 (GPTCTL1)
GPT Control Register 2 (GPTCTL2)
GPT Interrupt Enable Register (GPTIE)
GPT System Control Register 2 (GPTSCR2)
GPT Flag Register 1 (GPTFLG1)
GPT Flag Register 2 (GPTFLG2)
MCF5282 User's Manual
Bits 7–0
2
Reserved
(2)
Reserved
1
Access
S
S
S
S
S
S
—
S
S
—
S
S
S
S
S
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