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Bits
12
11
10–8
7–5
4–0
2.2.3.2
Supervisor/User Stack Pointers (A7 and OTHER_A7)
The MCF5282 architecture supports two independent stack pointer (A7) registers
supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware
implementation of these two programmable-visible 32-bit registers does not identify one as
the SSP and the other as the USP. Instead, the hardware uses one 32-bit register as the active
A7 and the other as OTHER_A7. Thus, the register contents are a function of the processor
operation mode, as shown in the following:
if SR[S] = 1
then
A7 = Supervisor Stack Pointer
OTHER_A7 = User Stack Pointer
else
A7 = User Stack Pointer
OTHER_A7 = Supervisor Stack Pointer
The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It
is the responsibility of the external development system to determine, based on the setting
of SR[S], the mapping of A7 and OTHER_A7 to the two program-visible definitions (SSP
and USP). This functionality is enabled by setting the enable user stack pointer bit,
CACR[EUSP]. If this bit is cleared, only the stack pointer (A7), defined for previous
ColdFire versions, is available. EUSP is zero at reset.
If EUSP is set, the appropriate stack pointer register (SSP or USP) is accessed as a function
of the processor's operating mode. To support dual stack pointers, the following two
privileged M68000 instructions are added to the ColdFire instruction set architecture to
load/store the USP :
move.l Ay, USP; move to USP
move.l USP, Ax; move from USP
These instructions are described in the ColdFire Family Programmer's Reference Manual.
MOTOROLA
Table 2-2. SR Field Descriptions (continued)
Name
M
Master/interrupt state. This bit is cleared by an interrupt exception, and
can be set by software during execution of the RTE or move to SR
instructions.
—
Reserved, should be cleared.
I
Interrupt level mask. Defines the current interrupt level. Interrupt
requests are inhibited for all priority levels less than or equal to the
current level, except the edge-sensitive level 7 request, which cannot
be masked.
—
Reserved, should be cleared.
CCR
Refer to Table 2-1.
Chapter 2. ColdFire Core
Processor Register Description
Description
the
—
2-7
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