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16 bytes of commands.
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR] and
causes the value in QAR to increment. Correspondingly, a read at QDR returns the data in
the RAM at the address specified by QAR[ADDR]. This also causes QAR to increment. A
read access requires a single wait state.
22.4.1.1 Receive RAM
Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F
in the QSPI RAM space. The user reads this segment to retrieve data from the QSPI. Data
words with less than 16 bits are stored in the least significant bits of the RAM. Unused bits
in a receive queue entry are set to zero upon completion of the individual queue entry.
QWR[CPTQP] shows which queue entries have been executed. The user can query this
field to determine which locations in receive RAM contain valid data.
MOTOROLA
Chapter 22. Queued Serial Peripheral Interface (QSPI) Module
Relative Address
Register
0x00
QTR0
0x01
QTR1
.
.
.
.
.
.
0x0F
QTR15
0x10
QRR0
0x11
QRR1
.
.
.
.
.
.
0x1F
QRR15
0x20
QCR0
0x21
QCR1
.
.
.
.
.
.
0x2F
QCR15
Figure 22-2. QSPI RAM Model
Function
Transmit RAM
16 bits wide
Receive RAM
16 bits wide
Command RAM
8 bits wide
Operation
22-5
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