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FF1
Operation:
Assembler Syntax:
Attributes:
Instruction
15
14
Format:
0
0
The data register, Dx, is scanned, beginning from the most-significant bit (Dx[31]) and
ending with the least-significant bit (Dx[0]), searching for the first set bit. The data register
is then loaded with the offset count from bit 31 where the first set bit appears, as shown
below. If the source data is zero, then an offset of 32 is returned.
Condition
X
—
Codes:
Instruction Field:
•
Destination Register field—Specifies the destination data register, Dx.
FF1
Opcode present
MOTOROLA
Find First One in Register
(Supported Starting with ISA A+)
Bit Offset of the First Logical One in Register → Destination
FF1.L Dx
Size = longword
13
12
11
10
0
0
0
1
Old Dx[31:0]
0b1---- . . . ----
0b01--- . . . ----
0b001-- . . . ----
...
0b00000 . . . 0010
0b00000 . . . 0001
0b00000 . . . 0000
N
Z
V
C
∗
∗
0
0
V2, V3 Core (ISA_A)
Chapter 2. ColdFire Core
ColdFire Instruction Set Architecture Enhancements
9
8
7
6
0
0
1
1
New Dx[31:0]
0x0000 0000
0x0000 0001
0x0000 0002
...
0x0000 001E
0x0000 001F
0x0000 0020
X Not affected
N Set if the msb of the source operand is set; cleared
otherwise
Z Set if the source operand is zero; cleared otherwise
V Always cleared
C Always cleared
V4 Core (ISA_B)
No
No
FF1
5
4
3
2
1
0
0
0
Destination
Register, Dx
V2 Core (ISA_A+)
Yes
0
2-31
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