Uart Mode Register 2 (Umr2N); Umr2N Field Descriptions - Motorola ColdFire MCF5281 User Manual

Register Descriptions

23.3.2 UART Mode Register 2 (UMR2n)

The UMR2n registers control UART module configuration. UMR2n can be read or written
when the mode register pointer points to it, which occurs after any access to UMR1n.
UMR2n accesses do not update the pointer.
7
Field CM
Reset
R/W
Address IPSBAR + 0x200 (UART0), 0x240 (UART1), 0x280 (UART2). After UMR1n is read or written, the pointer points to
Table 23-3 describes UMR2n fields.
Bits Name
7–6 CM Channel mode. Selects a channel mode. Section 23.5.3, "Looping Modes," describes individual modes.
00 Normal
01 Automatic echo
10 Local loop-back
11 Remote loop-back
5 TxRTS Transmitter ready-to-send. Controls negation of RTS to automatically terminate a message transmission.
Attempting to program a receiver and transmitter in the same channel for RTS control is not permitted and disables
RTS control for both.
0 The transmitter has no effect on RTS.
1 In applications where the transmitter is disabled after transmission completes, setting this bit automatically
clears UOP[RTS] one bit time after any characters in the channel transmitter shift and holding registers are
completely sent, including the programmed number of stop bits.
4 TxCTS Transmitter clear-to-send. If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the transmitter.
0 CTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character.
If CTS is asserted, the character is sent; if it is negated, the channel TXD remains in the high state and
transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its
transmission.
23-6
6 5
TxRTS TxCTS
Figure 23-3. UART Mode Register 2 (UMR2n)
Table 23-3. UMR2n Field Descriptions
MCF5282 User's Manual
4 3
0000_0000
R/W
UMR2n.
Description
0
SB
MOTOROLA