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Memory Map and Registers
Bit(s)
Name
15–0
CNTR
20.5.6 GPT System Control Register 1 (GPTSCR1)
Field
GPTEN
Reset
R/W
Address
Figure 20-7. GPT System Control Register 1 (GPTSCR1)
Bit(s)
Name
7
GPTEN
6–5
—
4
TFFCA
3–0
—
20-8
Table 20-8. GPTCNT Field Descriptions
Read-only field that provides the current count of the timer counter. To ensure coherent
reading of the timer counter, such that a timer rollover does not occur between two
back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used.
A write to GPTCNT may have an extra cycle on the first count because the write is not
synchronized with the prescaler clock. The write occurs at least one cycle before the
synchronization of the prescaler clock.
These bits are read anytime. They should be written to only in test (special) mode;
writing to them has no effect in normal modes.
7
6
5
—
IPSBAR + 0x1A_0006, 0x1B_0006
Table 20-9. GPTSCR1 Field Descriptions
Enables the general purpose timer. When the timer is disabled, only the registers are
accessible. Clearing GPTEN reduces power consumption. These bits are read
anytime, write anytime.
1 GPT enabled
0 GPT and GPT counter disabled
Reserved, should be cleared.
Timer fast flag clear all. Enables fast clearing of the main timer interrupt flag registers
(GPTFLG1 and GPTFLG2) and the PA flag register (GPTPAFLG). TFFCA eliminates
the software overhead of a separate clear sequence. See Figure 20-8.
When TFFCA is set:
• An input capture read or a write to an output compare channel clears the
corresponding channel flag, CxF.
• Any access of the GPT count registers (GPTCNTH/L) clears the TOF flag.
• Any access of the PA counter registers (GPTPACNT) clears both the PAOVF and
PAIF flags in GPTPAFLG.
Writing logic 1s to the flags clears them only when TFFCA is clear.
1 Fast flag clearing
0 Normal flag clearing
Reserved, should be cleared.
MCF5282 User's Manual
Description
4
3
TFFCA
0000_0000
R/W
Description
0
—
MOTOROLA
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