Motorola ColdFire MCF5281 Manuals

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Motorola ColdFire MCF5281 User Manual

Motorola ColdFire MCF5281 User Manual (816 pages)

Motorola Microcontroller User's Manual

Brand: Motorola | Category: Microcontrollers | Size: 9.86 MB

Table of Contents

Table of Contents
5
About this Book
43
General Information
46
Suggested Reading
46
Acronyms and Abbreviations
48
Revision History
52
Chapter 1 Overview

57
- MCF5282 Key Features
  57
- MCF5282 Block Diagram
  63
- Version 2 Coldfire Core
  64
- Cache Configuration
  64
- System Control Module
  66
- External Interface Module (EIM)
  66
- Chip Select
  67
- Power Management
  67
- General Input/Output Ports
  67
- Interrupt Controllers (INTC0/INTC1)
  67
- SDRAM Controller
  67
- Test Access Port
  68
- UART Modules
  68
- DMA Timers (DTIM0-DTIM3)
  69
- General-Purpose Timers (GPTA/GPTB)
  69
- Periodic Interrupt Timers (PIT0-PIT3)
  69
- Software Watchdog Timer
  70
- Phase Locked Loop (PLL)
  70
- DMA Controller
  70
- Reset
  70
- MCF5282-Specific Features
  71
- Fast Ethernet Controller (FEC)
  71
- Flexcan
  71
- I 2 C Bus
  71
- Queued Serial Peripheral Interface (QSPI)
  71
- Queued Analog-To-Digital Converter (QADC)
  71
Chapter 2 Coldfire Core

73
- Processor Pipelines
  73
- Coldfire Processor Core Pipelines
  73
- Processor Register Description
  74
- User Programming Model
  74
- User Programming Model
  76
- Condition Code Register (CCR)
  76
- CCR Field Descriptions
  76
- EMAC Programming Model
  77
- Supervisor Programming Model
  77
- EMAC Register Set
  77
- Supervisor Programming Model
  78
- Status Register
  78
- SR Field Descriptions
  78
- Programming Model
  80
- Coldfire CPU Registers
  80
- Additions to the Instruction Set Architecture
  81
- Exception Processing Overview
  82
- ISA Revision A+ New Instructions
  82
- Exception Vector Assignments
  83
- Exception Stack Frame Definition
  84
- Exception Stack Frame Form
  84
- Format Field Encodings
  84
- Processor Exceptions
  85
- Access Error Exception
  85
- Fault Status Encodings
  85
- Address Error Exception
  86
- Illegal Instruction Exception
  86
- Divide-By-Zero
  86
- Privilege Violation
  86
- Trace Exception
  86
- Unimplemented Line-A Opcode
  87
- Unimplemented Line-F Opcode
  87
- Debug Interrupt
  87
- RTE and Format Error Exception
  88
- TRAP Instruction Exception
  88
- Interrupt Exception
  88
- Fault-On-Fault Halt
  88
- Reset Exception
  88
- D0 Hardware Configuration Info
  89
- D0 Hardware Configuration Info Field Description
  90
- D1 Hardware Configuration Info
  91
- Instruction Execution Timing
  93
- Timing Assumptions
  93
- MOVE Instruction Execution Times
  94
- Misaligned Operand References
  94
- Move Byte and Word Execution Times
  95
- Move Long Execution Times
  95
- Standard One Operand Instruction Execution Times
  96
- Standard Two Operand Instruction Execution Times
  96
- Miscellaneous Instruction Execution Times
  98
- EMAC Instruction Execution Times
  99
- Branch Instruction Execution Times
  100
- Coldfire Instruction Set Architecture Enhancements
  100
- General Branch Instruction Execution Times
  100
- BRA, Bcc Instruction Execution Times
  100
Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC)

105
- Multiply-Accumulate Unit
  105
- Introduction to the MAC
  106
- Multiply-Accumulate Functionality Diagram
  106
- General Operation
  107
- Infinite Impulse Response (IIR) Filter
  107
- Four-Tap FIR Filter
  107
- Fractional Alignment
  108
- Signed and Unsigned Integer Alignment
  108
- Memory Map/Register Set
  110
- MAC Status Register (MACSR)
  110
- EMAC Register Set
  110
- MACSR Field Descriptions
  111
- Summary of S/U, F/I, and R/T Control Bits
  112
- Mask Register (MASK)
  114
- EMAC Instruction Set Summary
  116
- EMAC Instruction Execution Times
  116
- EMAC Instruction Summary
  116
- Data Representation
  117
- EMAC-Specific OEP Sequence Stall
  117
- MAC Opcodes
  118
- Two's Complement, Signed Fractional Equation
  118
Chapter 4

125
- Cache Features
  125
- Cache Physical Organization
  125
- Cache Operation
  127
- Interaction with Other Modules
  127
- Cache Block Diagram
  127
- Memory Reference Attributes
  128
- Cache Coherency and Invalidation
  128
- Reset
  129
- Cache Miss Fetch Algorithm/Line Fills
  129
- Initial Fetch Offset Vs. CLNF Bits
  129
- Instruction Cache Operation as Defined by CACR[31, 10]
  130
- Cache Programming Model
  131
- Cache Registers Memory Map
  131
- Cache Registers
  131
- Cache Control Register (CACR)
  132
- CACR Field Descriptions
  132
- Cache Configuration as Defined by CACR[31, 23, 22]
  134
- Cache Invalidate All as Defined by CACR[23, 22, 21, 20]
  134
- Access Control Registers (ACR0, ACR1)
  135
- External Fetch Size Based on Miss Address and CLNF
  135
- ACR Field Descriptions
  135
Chapter 5 Static RAM (SRAM)

137
- SRAM Features
  137
- SRAM Operation
  137
- SRAM Programming Model
  137
- SRAM Base Address Register (RAMBAR)
  138
- SRAM Initialization
  139
- SRAM Initialization Code
  140
- Power Management
  140
- Typical RAMBAR Setting Examples
  140
Chapter 6 Coldfire Flash Module (CFM)

143
- Features
  143
- Block Diagram
  144
- CFM Block Diagram
  145
- Memory Map
  146
- CFM Array Memory Map
  146
- CFM Configuration Field
  147
- Flash Base Address Register (FLASHBAR)
  147
- Flash Base Address Register (FLASHBAR)
  149
- FLASHBAR Field Descriptions
  149
- CFM Registers
  150
- Register Descriptions
  150
- CFM Module Configuration Register (CFMCR)
  150
- CFM Register Address Map
  150
- CFM Clock Divider Register (CFMCLKD)
  151
- CFMCR Field Descriptions
  151
- CFM Security Register (CFMSEC)
  152
- CFMCLKD Field Descriptions
  152
- CFMSEC Field Descriptions
  153
- CFM Protection Register (CFMPROT)
  154
- CFMPROT Field Descriptions
  154
- CFMPROT Protection Diagram
  155
- CFM Supervisor Access Register (CFMSACC)
  155
- CFM Data Access Register (CFMDACC)
  156
- CFMSACC Field Descriptions
  156
- CFMDACC Field Descriptions
  156
- CFM User Status Register (CFMUSTAT)
  157
- CFMUSTAT Field Descriptions
  157
- CFM Command Register (CFMCMD)
  158
- CFMCMD Field Descriptions
  158
- CFMCMD User Mode Commands
  158
- CFM Operation
  159
- Read Operations
  159
- Write Operations
  159
- Program and Erase Operations
  159
- Flash User Commands
  162
- Example Program Algorithm
  163
- Stop Mode
  164
- Master Mode
  165
- Flash Security Operation
  165
- Back Door Access
  166
- Erase Verify Check
  166
- Reset
  166
- Interrupts
  167
- CFM Interrupt Sources
  167
Chapter 7 Power Management

169
- Features
  169
- Memory Map and Registers
  169
- Programming Model
  169
- Memory Map
  170
- Register Descriptions
  170
- Low-Power Interrupt Control Register (LPICR)
  171
- LPICR Field Description
  171
- Low-Power Control Register (LPCR)
  172
- XLPM_IPL Settings
  172
- LPCR Field Descriptions
  172
- Functional Description
  173
- Low-Power Modes
  173
- PLL/CLKOUT Stop Mode Operation
  173
- Wait Mode
  174
- Peripheral Behavior in Low-Power Modes
  175
- Reset Controller
  178
- Clock Module
  179
- Watchdog Timer
  180
- Summary of Peripheral State During Low-Power Modes
  184
- CPU and Peripherals in Low-Power Modes
  184
Chapter 8 System Control Module (SCM)

187
- Overview
  187
- Features
  187
- Memory Map and Register Definition
  188
- SCM Register Map
  188
- Register Descriptions
  189
- Internal Peripheral System Base Address Register (IPSBAR)
  189
- Memory Base Address Register (RAMBAR)
  190
- IPS Base Address Register (IPSBAR)
  190
- IPSBAR Field Description
  190
- RAMBAR Field Description
  191
- Memory Base Address Register (RAMBAR)
  191
- Core Reset Status Register (CRSR)
  192
- Core Watchdog Control Register (CWCR)
  192
- CRSR Field Descriptions
  192
- Core Watchdog Control Register (CWCR)
  194
- CWCR Field Description
  194
- Core Watchdog Timer Delay
  194
- Core Watchdog Service Register (CWSR)
  195
- Internal Bus Arbitration
  195
- Arbiter Module Functions
  196
- Overview
  197
- Arbitration Algorithms
  197
- Bus Master Park Register (MPARK)
  198
- Default Bus Master Park Register (MPARK)
  198
- MPARK Field Description
  199
- System Access Control Unit (SACU)
  200
- Overview
  200
- Features
  200
- Memory Map/Register Definition
  201
- SACU Register Memory Map
  201
- Master Privilege Register (MPR)
  202
- Mpr[N] Field Descriptions
  202
- Peripheral Access Control Register (Pacrn)
  203
- PACR Field Descriptions
  203
- PACR ACCESSCTRL Bit Encodings
  203
- Peripheral Access Control Registers (Pacrs)
  203
- GPACR Register
  204
- GPACR ACCESS_CTRL Bit Encodings
  205
- GPACR Address Space
  206
Chapter 9 Clock Module

207
- Features
  207
- Modes of Operation
  207
- Normal PLL Mode
  207
- 1:1 PLL Mode
  208
- External Clock Mode
  208
- Low-Power Mode Operation
  208
- Clock Module Operation in Low-Power Modes
  208
- Block Diagram
  209
- Signal Descriptions
  210
- Extal
  210
- PLL Block Diagram
  210
- Signal Properties
  210
- Xtal
  211
- Clkout
  211
- Clkmod[1:0]
  211
- Rstout
  211
- Memory Map and Registers
  211
- Module Memory Map
  211
- Clock Module Memory Map
  211
- Synthesizer Control Register (SYNCR)
  212
- Register Descriptions
  212
- SYNCR Field Descriptions
  212
- Synthesizer Status Register (SYNSR)
  214
- SYNSR Field Descriptions
  215
- Functional Description
  216
- System Clock Modes
  216
- Clock Operation During Reset
  217
- System Clock Generation
  217
- Clock out and Clock in Relationships
  217
- PLL Operation
  218
- Crystal Oscillator Example
  218
- Charge Pump Current and MFD in Normal Mode Operation
  219
- Lock Detect Sequence
  221
- Loss of Clock Summary
  222
- Stop Mode Operation
  223
Chapter 10 Interrupt Controller Modules

229
Chapter 11

248
- Interrupt/General-Purpose I/O Pin Descriptions
  248
- Edge Port Module Operation in Low-Power Modes
  248
  - Registers
    249
  - Memory Map and Registers
    249
- Edge Port Module Memory Map
  249
- EPORT Pin Assignment Register (EPPAR)
  250
- EPORT Data Direction Register (EPDDR)
  250
- EPPAR Field Descriptions
  250
- EPORT Port Interrupt Enable Register (EPIER)
  251
- EPORT Port Data Register (EPDR)
  251
- EPDD Field Descriptions
  251
- EPIER Field Descriptions
  251
- EPORT Port Pin Data Register (EPPDR)
  252
- EPORT Port Flag Register (EPFR)
  252
- EPDR Field Descriptions
  252
- EPPDR Field Descriptions
  252
- EPFR Field Descriptions
  253
  - Chip Select Module Signals
    255
  - Overview
    255
- Byte Enables/Byte Write Enable Signal Settings
  256
- Chip Select Operation
  257
Chapter 12

257
- General Chip Select Operation
  257
- Connections for External Memory Port Sizes
  258
- Accesses by Matches in Csars and Dacrs
  258
- Chip Select Registers
  259
- D[19:18] External Boot Chip Select Configuration
  259
  - Chip Select Module Registers
    260
  - Chip Select Address Registers (Csarn)
    260
- Chip Select Mask Registers (Csmrn)
  261
- Csarn Field Description
  261
- Csmrn Field Descriptions
  261
- Chip Select Control Registers (Cscrn)
  262
- Cscrn Field Descriptions
  263
Chapter 13

265
- Bus and Control Signals
  265
- Features
  265
- Coldfire Bus Signal Summary
  265
- Bus Characteristics
  266
- Data Transfer Operation
  266
- Signal Relationship to CLKOUT for Non-DRAM Access
  266
  - Bus Cycle Execution
    267
- Connections for External Memory Port Sizes
  267
- Chip-Select Module Output Timing Diagram
  267
- Accesses by Matches in Cscrs and Dacrs
  268
  - Data Transfer Cycle States
    269
  - Data Transfer State Transition Diagram
    269
- Bus Cycle States
  269
- Read Cycle
  270
- Read Cycle Flowchart
  271
- Basic Read Bus Cycle
  271
- Write Cycle
  272
- Write Cycle Flowchart
  272
- Basic Write Bus Cycle
  272
  - Fast Termination Cycles
    273
  - Read Cycle with Fast Termination
    273
- Write Cycle with Fast Termination
  273
- Back-To-Back Bus Cycles
  274
  - Burst Cycles
    274
- Line Read Burst (2-1-1-1), External Termination
  275
- Allowable Line Access Patterns
  275
- Line Read Burst (2-1-1-1), Internal Termination
  276
- Line Read Burst (3-2-2-2), External Termination
  276
- Line Read Burst-Inhibited, Fast Termination, External Termination
  277
- Line Write Burst (2-1-1-1), Internal/External Termination
  277
- Misaligned Operands
  278
- Line Write Burst (3-2-2-2) with One Wait State
  278
- Line Write Burst-Inhibited
  278
- Example of a Misaligned Longword Transfer (32-Bit Port)
  279
- Example of a Misaligned Word Transfer (32-Bit Port)
  279
  - Overview
    281
  - MCF5282 Block Diagram with Signal Interfaces
    282
- MCF5282 Signal Description
  283
- MCF5282 Alphabetical Signal Index
  288
- MCF5282 Signals and Pin Numbers Sorted by Function
  291
- Single-Chip Mode
  297
Chapter 14

297
- External Boot Mode
  297
- Pin Reset States at Reset (Single-Chip Mode)
  297
- MCF5282 External Signals
  298
- Transfer Size Encoding
  300
  - SDRAM Controller Signals
    301
  - Chip Configuration Signals
    302
  - Clock and Reset Signals
    302
  - Ethernet Module Signals
    303
  - External Interrupt Signals
    303
    
    Queued Serial Peripheral Interface (QSPI) Signals
    305
    
    Flexcan Signals
    306
    
    UART Module Signals
    306
  - General Purpose Timer Signals
    307
  - DMA Timer Signals
    308
  - Analog-To-Digital Converter Signals
    309
  - Debug Support Signals
    310
  - Processor Status Encoding
    312
  - Test Signals
    312
  - Power and Reference Signals
    313
Chapter 15 Definitions

315
- Overview
  315
- Block Diagram and Major Components
  316
- Synchronous DRAM Controller Block Diagram
  316
- SDRAM Controller Operation
  317
- SDRAM Commands
  317
  - DRAM Controller Signals
    318
  - Memory Map for SDRAMC Registers
    318
- Synchronous DRAM Signal Connections
  318
- DRAM Controller Registers
  318
- DRAM Control Register (DCR)
  319
- DCR Field Descriptions
  319
- DRAM Address and Control Register (Dacrn)
  320
- Dacrn Field Descriptions
  320
- DRAM Controller Mask Registers (Dmrn)
  322
- Dmrn Field Descriptions
  322
  - General Synchronous Operation Guidelines
    323
- Generic Address Multiplexing Scheme
  323
- MCF5282 to SDRAM Interface (8-Bit Port,13-Column Address Lines)
  324
- MCF5282 to SDRAM Interface (16-Bit Port, 12-Column Address Lines)
  325
- MCF5282 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)
  326
- MCF5282 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
  327
- Connections for External Memory Port Sizes
  327
- SDRAM Hardware Connections
  327
- Burst Read SDRAM Access
  328
- Burst Write SDRAM Access
  329
- Auto-Refresh Operation
  330
- Initialization Sequence
  331
- Self-Refresh Operation
  331
- SDRAM Example
  333
- SDRAM Example Specifications
  333
  - SDRAM Interface Configuration
    334
  - DCR Initialization
    334
- Initialization Values for DCR
  334
- SDRAM Hardware Connections
  334
- DCR Initialization Values
  334
- DACR Initialization
  335
- SDRAM Configuration
  335
- DACR Register Configuration
  335
  - DACR Initialization Values
    335
  - DMR Initialization
    336
- DMR0 Register
  336
- DMR0 Initialization Values
  336
- Mode Register Initialization
  337
- Mode Register Mapping to MCF5282 A[31:0]
  337
  - Initialization Code
    338
  - Overview
    341
Chapter 16

342
- DMA Module Features
  342
- DMA Signal Diagram
  342
- DMA Request Control (DMAREQC)
  343
- DMA Request Control Register (DMAREQC)
  343
- DMAREQC Field Description
  343
- DMA Transfer Overview
  344
- Dual-Address Transfer
  344
  - DMA Controller Module Programming Model
    345
  - Memory Map for DMA Controller Module Registers
    345
- Source Address Registers (Sarn)
  346
- Destination Address Registers (Darn)
  346
  - Byte Count Registers (BCR0–BCR3)
    347
    
    Byte Count Registers (Bcrn)—Bcr24Bit = 1
    347
    
    Byte Count Registers (Bcrn)—Bcr24Bit = 0
    347
- DMA Control Registers (Dcrn)
  348
- Dcrn Field Descriptions
  348
- DMA Status Registers (Dsrn)
  350
- Dsrn Field Descriptions
  350
- DMA Controller Module Functional Description
  351
  - Transfer Requests (Cycle-Steal and Continuous Modes)
    351
  - Data Transfer Modes
    352
  - Channel Initialization and Startup
    353
  - Data Transfer
    354
  - Termination
    355
    
    Overview
    357
    
    Features
    357
Chapter 17

358
- Full and Half Duplex Operation
  358
- Modes of Operation
  358
- Interface Options
  358
- Address Recognition Options
  359
- Internal Loopback
  359
- FEC Top-Level Functional Diagram
  360
- FEC Block Diagram
  360
  - Functional Description
    361
  - Initialization Sequence
    362
- ECR[ETHER_EN] De-Assertion Effect on FEC
  362
- User Initialization (before ECR[ETHER_EN])
  362
- Microcontroller Initialization
  363
  - User Initialization (after Asserting ECR[ETHER_EN])
    363
- FEC User Initialization (before ECR[ETHER_EN])
  363
  - Network Interface Options
    364
- MII Mode
  364
- Wire Mode Configuration
  364
  - FEC Frame Transmission
    365
  - FEC Frame Reception
    366
- Ethernet Address Recognition
  367
- Destination Address to 6-Bit Hash
  370
  - Full Duplex Flow Control
    372
- PAUSE Frame Field Specification
  372
  - Inter-Packet Gap (IPG) Time
    373
  - Collision Handling
    373
  - Internal and External Loopback
    373
  - Ethernet Error-Handling Procedure
    374
  - Transmission Errors
    374
  - Transmitter Underrun
    374
  - Retransmission Attempts Limit Expired
    374
  - Reception Errors
    375
  - Top Level Module Memory Map
    376
  - Programming Model
    376
  - Detailed Memory Map (Control/Status Registers)
    376
- FEC Register Memory Map
  376
  - MIB Block Counters Memory Map
    377
- MIB Counters Memory Map
  378
  - Registers
    379
- Ethernet Interrupt Event Register (EIR)
  380
- EIR Field Descriptions
  380
- Interrupt Mask Register (EIMR)
  382
- EIMR Field Descriptions
  382
- Receive Descriptor Active Register (RDAR)
  383
- RDAR Field Descriptions
  383
- Transmit Descriptor Active Register (TDAR)
  384
- Ethernet Control Register (ECR)
  384
- TDAR Field Descriptions
  384
- MII Management Frame Register (MMFR)
  385
- ECR Field Descriptions
  385
- MMFR Field Descriptions
  386
- MII Speed Control Register (MSCR)
  387
- MSCR Field Descriptions
  387
- MIB Control Register (MIBC)
  388
- Programming Examples for MSCR
  388
- MIBC Field Descriptions
  388
- Receive Control Register (RCR)
  389
- RCR Field Descriptions
  389
- Transmit Control Register (TCR)
  390
- TCR Field Descriptions
  391
- Physical Address Low Register (PALR)
  392
- Physical Address High Register (PAUR)
  392
- PALR Field Descriptions
  392
- Opcode/Pause Duration Register (OPD)
  393
- PAUR Field Descriptions
  393
- OPD Field Descriptions
  393
- Descriptor Individual Upper Address Register (IAUR)
  394
- Descriptor Individual Lower Address Register (IALR)
  394
- IAUR Field Descriptions
  394
- Descriptor Group Upper Address Register (GAUR)
  395
- IALR Field Descriptions
  395
- GAUR Field Descriptions
  395
- Descriptor Group Lower Address Register (GALR)
  396
- FIFO Transmit FIFO Watermark Register (TFWR)
  396
- GALR Field Descriptions
  396
- FIFO Receive Bound Register (FRBR)
  397
- TFWR Field Descriptions
  397
- FRBR Field Descriptions
  397
- FIFO Receive Start Register (FRSR)
  398
- FRSR Field Descriptions
  398
  - Receive Descriptor Ring Start (Erdsr)
    398
- Receive Descriptor Ring Start Register (ERDSR)
  399
- Transmit Buffer Descriptor Ring Start Register (ETDSR)
  399
- ERDSR Field Descriptions
  399
- Receive Buffer Size Register (EMRBR)
  400
- ETDSR Field Descriptions
  400
- EMRBR Field Descriptions
  400
- Buffer Descriptors
  401
  - Driver/Dma Operation with Buffer Descriptors
    401
  - Ethernet Receive Buffer Descriptor (Rxbd)
    403
- Receive Buffer Descriptor Field Definitions
  404
  - Ethernet Transmit Buffer Descriptor (Txbd)
    405
- Transmit Buffer Descriptor (Txbd)
  406
- Transmit Buffer Descriptor Field Definitions
  406
  - Low-Power Mode Operation
    409
  - Introduction
    409
- Watchdog Module Operation in Low-Power Modes
  409
  - Signals
    410
  - Block Diagram
    410
  - Memory Map and Registers
    410
  - Watchdog Timer Block Diagram
    410
- Watchdog Control Register (WCR)
  411
Chapter 18 Registers

411
- Watchdog Timer Module Memory Map
  411
- Watchdog Modulus Register (WMR)
  412
- WCR Field Descriptions
  412
- Watchdog Count Register (WCNTR)
  413
- WMR Field Descriptions
  413
- WCNTR Field Descriptions
  413
- Watchdog Service Register (WSR)
  414
- PIT Block Diagram
  415
- Overview
  415
- PIT Module Operation in Low-Power Modes
  416
  - Low-Power Mode Operation
    416
  - Signals
    416
- Programmable Interrupt Timer Modules Memory Map
  417
- Memory Map and Registers
  417
- PIT Control and Status Register (PCSR)
  418
- PCSR Field Descriptions
  418
  - Set-And-Forget Timer Operation
    420
  - Functional Description
    420
- PIT Modulus Register (PMR)
  420
- PIT Count Register (PCNTR)
  420
  - Free-Running Timer Operation
    421
  - Timeout Specifications
    421
- Counter Reloading from the Modulus Latch
  421
- Counter in Free-Running Mode
  421
- Interrupt Operation
  422
- PIT Interrupt Requests
  422
- Features
  423
- GPT Block Diagram
  424
  - Signal Description
    425
  - Low-Power Mode Operation
    425
- Gptn[2:0]
  425
- Watchdog Module Operation in Low-Power Modes
  425
- Signal Properties
  425
- Gptn3
  426
- Syncn
  426
- Memory Map and Registers
  426
- GPT Modules Memory Map
  426
- GPT Input Capture/Output Compare Select Register (GPTIOS)
  427
- GPT Compare Force Register (GPCFORC)
  428
- GPT Input Compare Force Register (GPCFORC)
  428
- GPTIOS Field Descriptions
  428
- GPTCFORC Field Descriptions
  428
- Gpt Output Compare 3 Mask Register (Gptoc3M)
  428
- GPTOC3M Field Descriptions
  429
- GPTOC3D Field Descriptions
  429
- Gpt Output Compare 3 Data Register (Gptoc3D)
  429
- Gpt Counter Register (Gptcnt)
  429
- GPTCNT Field Descriptions
  430
- GPTSCR1 Field Descriptions
  430
- Gpt System Control Register 1 (Gptscr)
  430
- Fast Clear Flag Logic
  431
- GPTTOV Field Description
  431
- Gpt Toggle-On-Overflow Register (Gpttov)
  431
- Gpt Control Register 1 (Gptctl)
  431
- GPTCL1 Field Descriptions
  432
- GPTLCTL2 Field Descriptions
  432
- Gpt Control Register 2 (Gptctl)
  432
- Gpt Interrupt Enable Register (Gptie)
  432
- GPTIE Field Descriptions
  433
- GPTSCR2 Field Descriptions
  433
- Gpt System Control Register 2 (Gptscr)
  433
- GPTFLG1 Field Descriptions
  434
- GPTFLG2 Field Descriptions
  434
- Gpt Flag Register 1 (Gptflg)
  434
- Gpt Flag Register 2 (Gptflg)
  434
- GPT Channel Registers (Gptcn)
  435
- Pulse Accumulator Control Register (GPTPACTL)
  435
- GPT Channel[0:3] Register (Gptcn)
  435
- Gptcn Field Descriptions
  435
- GPTPACTL Field Descriptions
  435
- Pulse Accumulator Flag Register (GPTPAFLG)
  436
- Pulse Accumulator Counter Register (GPTPACNT)
  437
- GPTPAFLG Field Descriptions
  437
- GPTPACR Field Descriptions
  437
- GPT Port Data Register (GPTPORT)
  438
- GPT Port Data Direction Register (GPTDDR)
  438
- GPTPORT Field Descriptions
  438
- GPTDDR Field Descriptions
  438
  - Prescaler
    439
- Functional Description
  439
- Input Capture
  439
- Output Compare
  439
- Pulse Accumulator
  440
- Event Counter Mode
  440
- Gated Time Accumulation Mode
  441
- General-Purpose I/O Ports
  441
- Channel 3 Output Compare/Pulse Accumulator Logic
  441
- GPT Settings and Pin Functions
  442
- GPT Interrupt Requests
  443
  - Reset
    443
  - Interrupts
    443
- GPT Channel Interrupts (Cnf)
  444
- Pulse Accumulator Overflow (PAOVF)
  444
- Pulse Accumulator Input (PAIF)
  444
- Timer Overflow (TOF)
  444
- Overview
  447
Chapter 21 Key Features

448
- DMA Timer Programming Model
  448
- Prescaler
  448
- DMA Timer Block Diagram
  448
  - Capture Mode
    449
  - Reference Compare
    449
  - Output Mode
    449
- DMA Timer Module Memory Map
  449
  - DMA Timer Mode Registers (Dtmrn)
    450
- Dtmrn Bit Definitions
  450
  - DMA Timer Extended Mode Registers (Dtxmrn)
    451
- Dtxmrn Bit Definitions
  451
- Dtmrn Field Descriptions
  451
  - DMA Timer Event Registers (Dtern)
    452
- Dtern Bit Definitions
  452
  - DMA Timer Reference Registers (Dtrrn)
    453
  - DMA Timer Capture Registers (Dtcrn)
    453
- Dtrrn Bit Definitions
  453
- Dtern Field Descriptions
  453
  - DMA Timer Counters (Dtcnn)
    454
- Using the DMA Timer Modules
  454
- Dtcrn Bit Definitions
  454
- Dtcnn Bit Definitions
  454
  - Code Example
    455
  - Calculating Time-Out Values
    456
- Module Description
  457
  - Overview
    457
  - Features
    457
Chapter 22

458
- Interface and Signals
  458
- QSPI Block Diagram
  458
  - Internal Bus Interface
    459
  - Operation
    459
- QSPI Input and Output Signals and Functions
  459
  - Qspi Ram
    460
- QSPI RAM Model
  461
  - Baud Rate Selection
    462
  - Transfer Delays
    463
- QSPI_CLK Frequency as Function of System Clock and Baud Rate
  463
  - Transfer Length
    464
- Data Transfer
  464
- QSPI Registers
  465
- Programming Model
  465
- QSPI Mode Register (QMR)
  466
- QMR Field Descriptions
  466
- QSPI Delay Register (QDLYR)
  467
- QSPI Clocking and Data Transfer Example
  467
- QSPI Wrap Register (QWR)
  468
- QDLYR Field Descriptions
  468
- QWR Field Descriptions
  468
- QSPI Interrupt Register (QIR)
  469
- QIR Field Descriptions
  469
- QSPI Data Register (QDR)
  470
- QSPI Address Register
  470
- Command RAM Registers (QCR0–QCR15)
  471
- QCR0–QCR15 Field Descriptions
  471
- Programming Example
  472
- QSPI Timing
  472
- Simplified Block Diagram
  475
- Overview
  475
Chapter 23 Serial Module Overview

476
- UART Module Memory Map
  477
  - Register Descriptions
    477
- UART Mode Registers 1 (Umr1N)
  478
- Umr1N Field Descriptions
  479
- UART Mode Register 2 (Umr2N)
  480
- Umr2N Field Descriptions
  480
  - UART Status Registers (Usrn)
    481
- Usrn Field Descriptions
  481
  - UART Clock Select Registers (Ucsrn)
    482
  - UART Command Registers (Ucrn)
    483
- Ucsrn Field Descriptions
  483
- Ucrn Field Descriptions
  484
- UART Transmit Buffer (Utbn)
  486
- Uipcrn Field Descriptions
  486
- UART Auxiliary Control Register (Uacrn)
  487
- UART Interrupt Status/Mask Registers (Uisrn/Uimrn)
  487
- Uacrn Field Descriptions
  487
  - UART Baud Rate Generator Registers (Ubg1N/Ubg2N)
    488
- Uisrn/Uimrn Field Descriptions
  488
- UART Input Port Register (Uipn)
  489
- UART Output Port Command Registers (Uop1N/Uop0N)
  489
- Uipn Field Descriptions
  489
- UOP1/UOP0 Field Descriptions
  490
- UART Module Signal Definitions
  491
- UART Block Diagram Showing External and Internal Interface Signals
  491
  - Operation
    492
  - Transmitter/Receiver Clock Source
    492
- UART/RS-232 Interface
  492
- UART Module Signals
  492
- Clocking Source Diagram
  493
  - Transmitter and Receiver Operating Modes
    494
- Transmitter and Receiver Functional Diagram
  494
- Transmitter Timing Diagram
  496
- Receiver Timing
  497
  - Looping Modes
    499
- Automatic Echo
  499
- Local Loop-Back
  499
  - Multidrop Mode
    500
- Remote Loop-Back
  500
- Multidrop Mode Timing Diagram
  501
  - Bus Operation
    502
- Programming
  502
- UART Interrupts
  503
- UART DMA Requests
  504
- UART Module Initialization Sequence
  504
- UART Mode Programming Flowchart
  505
Chapter 24 Interface Features

511
- Overview
  511
- Arbitration Procedure
  514
- Repeated START
  514
  - Clock Synchronization
    515
  - Handshaking
    515
  - Clock Stretching
    515
- Synchronized Clock SCL
  515
- I2ADR Field Descriptions
  516
- Programming Model
  516
- I2FDR Field Descriptions
  517
- I2CR Field Descriptions
  518
- I2SR Field Descriptions
  519
  - Initialization Sequence
    520
  - Generation of START
    521
  - Post-Transfer Software Response
    521
  - Generation of STOP
    522
  - Generation of Repeated START
    523
  - Slave Mode
    523
  - Arbitration Lost
    524
  - Features
    527
- Flexcan Block Diagram and Pinout
  528
- Flexcan Memory Map
  529
Chapter 25 External Signals

529
- The CAN System
  530
  - Message Buffers
    530
  - Message Buffer Structure
    530
- Typical CAN System
  530
- Extended ID Message Buffer Structure
  531
- Standard ID Message Buffer Structure
  531
- Common Extended/Standard Format Frames
  532
- Message Buffer Codes for Receive Buffers
  532
- Message Buffer Codes for Transmit Buffers
  532
  - Message Buffer Memory Map
    533
- Extended Format Frames
  533
- Standard Format Frames
  533
- Functional Overview
  534
  - Flexcan Memory Map
    534
  - Receive Process
    535
  - Transmit Process
    535
  - Message Buffer Handling
    536
  - Self-Received Frames
    536
  - Remote Frames
    538
  - Listen-Only Mode
    539
  - Overload Frames
    539
  - Time Stamp
    539
  - Bit Timing
    540
- Examples of System Clock/Can Bit-Rate/S-Clock
  540
  - Flexcan Error Counters
    541
  - Flexcan Initialization Sequence
    542
  - Special Operating Modes
    543
  - Interrupts
    545
- Programmer's Model
  546
- CAN Module Configuration Register (CANMCR)
  546
- CANMCR Field Descriptions
  547
- Flexcan Control Register 0 (CANCTRL0)
  548
- Flexcan Control Register 1 (CANCTRL1)
  549
- CANCTRL0 Field Descriptions
  549
- Transmit Pin Configuration
  549
- Prescaler Divide Register (PRESDIV)
  550
- CANCTRL1 Field Descriptions
  550
- Flexcan Control Register 2 (CANCTRL2)
  551
- PRESDIV Field Descriptions
  551
- CANCTRL2 Field Descriptions
  551
  - Free Running Timer (TIMER)
    552
- Rx Mask Registers
  552
- TIMER Field Descriptions
  552
- Mask Examples for Normal/Extended Messages
  552
- Rx Mask Registers (RXGMASK, RX14MASK, and RX15MASK)
  553
- Flexcan Error and Status Register (ESTAT)
  554
- RXGMASK, RX14MASK, and RX15MASK Field Descriptions
  554
- ESTAT Field Descriptions
  555
- Interrupt Mask Register (IMASK)
  556
- Interrupt Flag Register (IFLAG)
  557
- IMASK Field Descriptions
  557
- IFLAG Field Descriptions
  557
- Flexcan Receive Error Counter (RXECTR)
  558
- Flexcan Transmit Error Counter (TXECTR)
  558
- RXECTR Field Descriptions
  558
- TXECTR Field Descriptions
  558
- Introduction
  559
- MCF5282 Ports Module Block Diagram
  560
- Overview
  561
Chapter 31

561
- Features
  561
- Modes of Operation
  561
- External Signal Description
  562
- MCF5282 Ports External Signals
  562
Chapter 26

564
- Register Overview
  564
- Memory Map/Register Definition
  564
- MCF5282 Ports Module Memory Map
  564
- Register Descriptions
  566
- Port Output Data Registers (6-Bit)
  566
- Port Output Data Registers (4-Bit)
  567
- Port Data Direction Registers (8-Bit)
  567
- Portn (8-Bit, 7-Bit, 6-Bit, and 4-Bit) Field Descriptions
  567
- Port Data Direction Register (7-Bit)
  568
- Port Data Direction Registers (4-Bit)
  568
- Ddrn (8-Bit, 6-Bit, and 4-Bit) Field Descriptions
  568
- Port Pin Data/Set Data Registers (6-Bit)
  569
- Port Pin Data/Set Data Registers (4-Bit)
  570
- Port Clear Output Data Registers (8-Bit)
  570
- Portnp/Setn (8-Bit, 6-Bit, and 4-Bit) Field Descriptions
  570
- Port Clear Output Data Register (7-Bit)
  571
- Port Clear Output Data Registers (4-Bit)
  571
- Clrn (8-Bit,7-Bit, 6-Bit, and 4-Bit) Field Descriptions
  571
- Port B/C/D Pin Assignment Register (PBCDPAR)
  572
- PBCDPAR Field Descriptions
  572
- Reset Values for PBCDPAR Bits
  572
- Port E Pin Assignment Register (PEPAR)
  573
- PEPAR Field Descriptions
  573
- Reset Values for PEPAR Bits and Fields
  574
- Port F Pin Assignment Register (PFPAR)
  575
- PFPAR Field Descriptions
  575
- Port J Pin Assignment Register (PJPAR)
  576
- PJPAR Field Descriptions
  576
- Port SD Pin Assignment Register (PSDPAR)
  577
- Port as Pin Assignment Register (PASPAR)
  577
- PSDPAR Field Descriptions
  577
- Port EH/EL Pin Assignment Register (PEHLPAR)
  578
- PASPAR Field Descriptions
  578
- Port QS Pin Assignment Register (PQSPAR)
  579
- PEHLPAR Field Descriptions
  579
- PQSPAR Field Description
  579
- Port TC Pin Assignment Register (PTCPAR)
  580
- PTCPAR Field Descriptions
  580
- Port TD Pin Assignment Register (PTDPAR)
  581
- PTDPAR Field Descriptions
  581
- Port UA Pin Assignment Register (PUAPAR)
  582
- PUAPAR Field Descriptions
  582
- Port Digital I/O Timing
  583
  - Functional Description
    583
  - Overview
    583
- Digital Input Timing
  583
- Initialization/Application Information
  584
- Digital Output Timing
  584
- Features
  585
- QADC Block Diagram
  586
  - Debug Mode
    587
  - Modes of Operation
    587
  - Stop Mode
    587
Chapter 27

588
- Port QA Signal Functions
  588
- Signals
  588
- Port QB Signal Functions
  589
- QADC Input and Output Signals
  589
- External Trigger Input Signals
  590
- Multiplexed Address Output Signals
  590
- Multiplexed Analog Input Signals
  590
- Voltage Reference Signals
  591
  - Dedicated Analog Supply Signals
    591
  - Dedicated Digital I/O Port Supply Signal
    591
  - Memory Map
    591
- Multiplexed Analog Input Channels
  591
- QADC Module Configuration Register (QADCMCR)
  592
- Register Descriptions
  592
- QADC Memory Map
  592
- QADCMCR Field Descriptions
  593
  - Port QA and QB Data Direction Register (DDRQA and DDRQB)
    594
- QADC Port QA Data Register (PORTQA)
  594
- QADC Port QB Data Register (PORTQB)
  594
  - Control Registers
    595
- QADC Port QA Data Direction Register (DDRQA)
  595
- Port QB Data Direction Register (DDRQB)
  595
- QADC Control Register 0 (QACR0)
  596
- QACR0 Field Descriptions
  596
- QADC Control Register 1 (QACR1)
  598
- QACR1 Field Descriptions
  598
- Queue 1 Operating Modes
  599
- QADC Control Register 2 (QACR2)
  601
- QACR2 Field Descriptions
  602
- Queue 2 Operating Modes
  602
  - Status Registers
    603
- QADC Status Register 0 (QASR0)
  606
- QASR0 Field Descriptions
  607
- CCW Pause Bit Response
  608
- Queue Status
  608
- Queue Status Transition
  609
- Conversion Command Word Table (CCW)
  610
- QADC Status Register 1 (QASR1)
  610
- QASR1 Field Descriptions
  610
- CCW Field Descriptions
  611
- Conversion Command Word Table (CCW)
  611
- Input Sample Times
  612
- Non-Multiplexed Channel Assignments and Signal Designations
  612
  - Result Registers
    613
- Right-Justified Unsigned Result Register (RJURR)
  613
- Multiplexed Channel Assignments and Signal Designations
  613
- Left-Justified Signed Result Register (LJSRR)
  614
- RJURR Field Descriptions
  614
- LJSRR Field Descriptions
  614
  - Result Coherency
    615
  - Functional Description
    615
- External Multiplexing
  615
- Left-Justified Unsigned Result Register (LJURR)
  615
- LJURR Field Descriptions
  615
  - External Multiplexing Configuration
    617
  - Analog Subsystem
    618
- Analog Input Channels
  618
- QADC Analog Subsystem Block Diagram
  619
- Conversion Timing
  620
- Bypass Mode Conversion Timing
  620
- Digital Control Subsystem
  621
  - Queue Priority Timing Examples
    622
- QADC Queue Operation with Pause
  623
- Trigger Events
  624
- Status Bits
  624
- CCW Priority Situation 1
  625
- CCW Priority Situation 2
  626
- CCW Priority Situation 3
  626
- CCW Priority Situation 4
  627
- CCW Priority Situation 5
  627
- CCW Priority Situation 6
  628
- CCW Priority Situation 7
  628
- CCW Priority Situation 8
  629
- CCW Priority Situation 9
  629
- CCW Priority Situation 10
  630
- CCW Priority Situation 11
  630
- CCW Freeze Situation 12
  631
- CCW Freeze Situation 13
  631
- CCW Freeze Situation 14
  631
- CCW Freeze Situation 15
  631
- CCW Freeze Situation 16
  632
- CCW Freeze Situation 17
  632
- CCW Freeze Situation 18
  632
- CCW Freeze Situation 19
  632
  - Boundary Conditions
    633
  - Scan Modes
    634
  - Disabled Mode
    634
  - Reserved Mode
    634
  - Single-Scan Modes
    634
  - Continuous-Scan Modes
    638
  - QADC Clock (QCLK) Generation
    641
  - Periodic/Interval Timer
    642
- QADC Clock Subsystem Functions
  642
  - Conversion Command Word Table
    643
- QADC Conversion Queue Operation
  644
  - Result Word Table
    646
- Signal Connection Considerations
  646
  - Analog Reference Signals
    647
  - Analog Power Signals
    647
- Equivalent Analog Input Circuitry
  647
- Conversion Timing Schemes
  648
- Errors Resulting from Clipping
  648
- External Positive Edge Trigger Mode Timing with Pause
  649
- Gated Mode, Single Scan Timing
  650
  - Analog Supply Filtering and Grounding
    651
- Gated Mode, Continuous Scan Timing
  651
- Star-Ground at the Point of Power Supply Origin
  652
  - Accommodating Positive/Negative Stress Conditions
    653
- Input Signal Subjected to Negative Stress
  653
- Input Signal Subjected to Positive Stress
  654
  - Analog Input Considerations
    655
- External Multiplexing of Analog Signal Sources
  656
  - Analog Input Pins
    657
- Electrical Model of an A/D Input Signal
  657
- External Circuit Settling Time to 1/2 LSB
  658
  - Interrupt Operation
    659
  - Interrupts
    659
  - Interrupt Sources
    660
- QADC Status Flags and Interrupt Sources
  660
- Features
  661
Chapter 19

662
- Signals
  662
  - Rsto
    662
  - Reset Controller Block Diagram
    662
  - Reset Controller Signal Properties
    662
  - Reset Control Register (RCR)
    663
  - Memory Map and Registers
    663
  - Reset Controller Memory Map
    663
- RCR Field Descriptions
  663
- Reset Status Register (RSR)
  664
- RSR Field Descriptions
  665
  - Reset Sources
    666
  - Functional Description
    666
- Reset Source Summary
  666
  - Watchdog Timer Reset
    667
  - Software Reset
    667
- Reset Control Flow
  668
  - Reset Control Flow
    669
  - Concurrent Resets
    670
- Processor/Debug Module Interface
  673
- Overview
  673
- CLKOUT Timing
  674
- Signal Description
  674
- Debug Module Signals
  674
- Real-Time Trace Support
  675
- Processor Status Encoding
  675
Chapter 28 RSTI

662
- Block Diagram
  662
Chapter 29

676
- Begin Execution of Taken Branch (PST = 0X5)
  676
- Example JMP Instruction Output on PST/DDATA
  677
- Programming Model
  677
- Debug Programming Model
  678
  - Revision a Shared Debug Resources
    679
- Bdm/Breakpoint Registers
  679
- Rev. a Shared Bdm/Breakpoint Hardware
  679
- Address Attribute Trigger Register (AATR)
  680
- AATR Field Descriptions
  680
- Address Breakpoint Registers (ABLR, ABHR)
  681
- Configuration/Status Register (CSR)
  682
- ABLR Field Description
  682
- ABHR Field Description
  682
- CSR Field Descriptions
  683
- Data Breakpoint/Mask Registers (DBR/DBMR)
  684
  - Program Counter Breakpoint/Mask Registers (PBR, PBMR)
    685
- DBR Field Descriptions
  685
- DBMR Field Descriptions
  685
- Access Size and Operand Data Location
  685
- Trigger Definition Register (TDR)
  686
- Program Counter Breakpoint Register (PBR)
  686
- Program Counter Breakpoint Mask Register (PBMR)
  686
- PBR Field Descriptions
  686
- PBMR Field Descriptions
  686
- TDR Field Descriptions
  687
- Trigger Definition Register (TDR)
  687
- Background Debug Mode (BDM)
  688
  - CPU Halt
    688
  - BDM Serial Interface
    690
- BDM Serial Interface Timing
  690
- Receive BDM Packet
  691
- Transmit BDM Packet
  691
  - Receive BDM Packet Field Description
    691
  - Transmit BDM Packet Field Description
    691
  - BDM Command Set
    692
- BDM Command Summary
  692
- BDM Command Format
  693
- BDM Field Descriptions
  693
- Command Sequence Diagram
  694
- NOP Command Format
  703
- Control Register Map
  704
- Definition of Drc Encoding—Read
  708
- Real-Time Debug Support
  709
  - Theory of Operation
    709
- DDATA[3:0]/CSR[BSTAT] Breakpoint Response
  709
  - Concurrent BDM and Processor Operation
    711
- Processor Status, DDATA Definition
  712
  - User Instruction Set
    712
- PST/DDATA Specification for User-Mode Instructions
  712
- PST/DDATA Specification for MAC Instructions
  715
  - Supervisor Instruction Set
    716
- PST/DDATA Specification for Supervisor-Mode Instructions
  716
- Recommended BDM Connector
  717
- Motorola-Recommended BDM Pinout
  718
- Features
  719
- Modes of Operation
  719
- Chip Configuration Module Block Diagram
  720
- Master Mode
  720
Chapter 30

720
- Single-Chip Mode
  720
- Rcon
  721
  - Clkmod[1:0]
    721
  - D[26:24, 21, 19:16] (Reset Configuration Override)
    721
  - Signal Descriptions
    721
- Memory Map and Registers
  721
- Programming Model
  721
- Signal Properties
  721
- Write-Once Bits Read/Write Accessibility
  722
  - Memory Map
    722
- Chip Configuration Module Memory Map
  722
- Chip Configuration Register (CCR)
  723
- Register Descriptions
  723
- CCR Field Descriptions
  723
  - Reset Configuration Register (RCON)
    724
  - RCON Field Descriptions
    724
- RCSC Chip Select Configuration
  725
- BOOTPS Port Size Configuration
  725
  - Reset Configuration
    726
  - Functional Description
    726
- Chip Identification Register (CIR)
  726
- CIR Field Description
  726
- Reset Configuration Pin States During Reset
  727
- Configuration During Reset
  727
  - Chip Mode Selection
    728
  - Boot Device Selection
    729
  - Output Pad Strength Configuration
    729
- Clock Mode Selection
  729
- Chip Configuration Mode Selection
  729
- Output Pad Driver Strength Selection
  729
  - Chip Select Configuration
    730
- Reset
  730
  - Interrupts
    730
  - Clock Mode Selection
    730
- JTAG Block Diagram
  732
  - Features
    732
  - Detailed Signal Description
    733
    
    External Signal Description
    733
    
    Modes of Operation
    733
    
    Signal Properties
    733
- Pin Function Selected
  733
- Signal State to the Disable Module
  734
- IDCODE Register
  735
  - Memory Map/Register Definition
    735
  - Register Descriptions
    735
- IDCODE Register Field Descriptions
  736
  - JTAG Module
    737
  - Functional Description
    737
- TAP Controller
  737
- JTAG Instructions
  738
  - TAP Controller State Machine Flow
    738
  - Initialization/Application Information
    741
  - Restrictions
    741
  - Nonscan Chain Operation
    742
Chapter 32 Mechanical Data

743
- Pinout
  744
- MCF5282 Pinout (256 MAPBGA)
  744
- MCF5282 Signal Description by Pin Number
  745
- Ordering Information
  749
- MAPBGA Package Dimensions
  749
- Orderable Part Numbers
  749
Chapter 33

751
- Maximum Ratings
  751
- Absolute Maximum Ratings
  751
- Thermal Characteristics
  753
- DC Electrical Specifications
  754
- Phase Lock Loop Electrical Specifications
  756
- PLL Electrical Specifications
  756
- QADC Electrical Characteristics
  757
- QADC Absolute Maximum Ratings
  757
- QADC Electrical Specifications (Operating)
  757
- Flash Memory Characteristics
  759
- QADC Conversion Specifications (Operating)
  759
- SGFM Flash Program and Erase Characteristics
  759
- External Interface Timing Characteristics
  760
- SGFM Flash Module Life Characteristics
  760
- Processor Bus Input Timing Specifications
  760
- Processor Bus Output Timing Specifications
  761
- General Input Timing Requirements
  761
- External Bus Output Timing Specifications
  761
- Read/Write (Internally Terminated) Timing
  763
- Read Bus Cycle Terminated by TA
  764
- Read Bus Cycle Terminated by TEA
  765
- SDRAM Read Cycle
  766
- SDRAM Timing
  766
- General Purpose I/O Timing
  767
- SDRAM Write Cycle
  767
  - GPIO Timing
    767
  - Reset and Configuration Override Timing
    768
- GPIO Timing
  768
- RSTI and Configuration Override Timing
  769
- Fast Ethernet AC Timing Specifications
  770
  - MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)
    771
- MII Receive Signal Timing Diagram
  771
- MII Receive Signal Timing
  771
- MII Transmit Signal Timing Diagram
  772
- MII Async Inputs Timing Diagram
  772
- MII Async Inputs Signal Timing
  772
- MII Serial Management Channel Timing Diagram
  773
- MII Serial Management Channel Timing
  773
- DMA Timer Module AC Timing Specifications
  774
- QSPI Electrical Specifications
  774
- QSPI Timing
  774
- QSPI Modules AC Timing Specifications
  774
- JTAG and Boundary Scan Timing
  775
- Test Clock Input Timing
  775
- Boundary Scan (JTAG) Timing
  776
- Test Access Port Timing
  776
- TRST Timing
  776
- Debug AC Timing Specifications
  777
- BKPT Timing
  777
- Real-Time Trace AC Timing
  778
- BDM Serial Port AC Timing
  778

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