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22.5.4 QSPI Interrupt Register (QIR)
Figure 22-7 shows the QIR register.
15
14
Field WCEFB ABRTB
Reset
R/W
Address
Table 22-7 describes QIR fields.
BIts
Name
15
WCEFB Write collision access error enable. A write collision occurs during a data transfer when the RAM
entry containing the command currently being executed is written to by the CPU with the QDR.
When this bit is asserted, the write access to QDR results in an access error.
14
ABRTB Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer. When
set, an attempt to clear QDLYR[SPE] during a transfer results in an access error.
13
—
Reserved, should be cleared.
12
ABRTL Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR. QDLYR[SPE]
is only cleared by the QSPI when a transfer completes.
11
WCEFE Write collision interrupt enable. Interrupt enable for WCEF. Setting this bit enables the interrupt, and
clearing it disables the interrupt.
10
ABRTE Abort interrupt enable. Interrupt enable for ABRT flag. Setting this bit enables the interrupt, and
clearing it disables the interrupt.
9
—
Reserved, should be cleared.
8
SPIFE
QSPI finished interrupt enable. Interrupt enable for SPIF. Setting this bit enables the interrupt, and
clearing it disables the interrupt.
7–4
—
Reserved, should be cleared.
3
WCEF
Write collision error flag. Indicates that an attempt has been made to write to the RAM entry that is
currently being executed. Writing a 1 to this bit clears it and writing 0 has no effect.
2
ABRT
Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the QDLYR rather
than by completion of the command queue by the QSPI. Writing a 1 to this bit clears it and writing
0 has no effect.
1
—
Reserved, should be cleared.
0
SPIF
QSPI finished flag. Asserted when the QSPI has completed all the commands in the queue. Set on
completion of the command pointed to by QWR[ENDQP], and on completion of the current
command after assertion of QWR[HALT]. In wraparound mode, this bit is set every time the
command pointed to by QWR[ENDQP] is completed. Writing a 1 to this bit clears it and writing 0
has no effect.
MOTOROLA
Chapter 22. Queued Serial Peripheral Interface (QSPI) Module
13
12
11
10
— ABRT
WCEFE ABRTE
L
0000_0000_0000_0000
IPSBAR + 0x34C
Figure 22-7. QSPI Interrupt Register (QIR)
Table 22-7. QIR Field Descriptions
9
8
7
— SPIFE
—
R/W
Description
Programming Model
4
3
2
1
0
WCEF ABRT — SPIF
22-13
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