Figure
Number
20-6
20-7
20-8
Fast Clear Flag Logic.................................................................................................. 20-9
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
20-21
20-22
21-1
DMA Timer Block Diagram....................................................................................... 21-2
21-2
DTMRn Bit Definitions .............................................................................................. 21-4
21-3
DTXMRn Bit Definitions ........................................................................................... 21-5
21-4
DTERn Bit Definitions ............................................................................................... 21-6
21-5
DTRRn Bit Definitions ............................................................................................... 21-7
21-6
DTCRn Bit Definitions ............................................................................................... 21-8
21-7
DTCNn Bit Definitions............................................................................................... 21-8
22-1
QSPI Block Diagram .................................................................................................. 22-2
22-2
QSPI RAM Model ...................................................................................................... 22-5
22-3
22-4
22-5
22-6
22-7
22-8
QSPI Address Register ............................................................................................. 22-14
22-9
22-10
22-11
QSPI Timing ............................................................................................................. 22-16
23-1
Simplified Block Diagram .......................................................................................... 23-1
23-2
23-3
23-4
UART Status Register (USRn) ................................................................................... 23-7
23-5
UART Clock Select Register (UCSRn)...................................................................... 23-8
23-6
UART Command Register (UCRn)............................................................................ 23-9
23-7
UART Receive Buffer (URBn) ................................................................................ 23-11
23-8
MOTOROLA
ILLUSTRATIONS
Title
Illustrations
Page
Number
xxvii