Clock Module - Motorola ColdFire MCF5281 User Manual

Motorola microcontroller user's manual
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Functional Description
If the phase lock loop (PLL) in the clock module is active and if the appropriate (LOCRE,
LOLRE) bits in the synthesizer control register are set, then any loss-of-clock or
loss-of-lock will reset the chip and exit any low-power modes.
If the watchdog timer is still enabled during wait or doze modes, then a watchdog timer
timeout may generate a reset to exit these low-power modes.
When the CPU is inactive, a software reset cannot be generated to exit any low-power
mode.
7.3.2.16 Chip Configuration Module
The Chip Configuration Module is unaffected by entry into a low-power mode. If
low-power mode is exited by a reset, chip configuration may be executed if configured to
do so.

7.3.2.17 Clock Module

In wait and doze modes, the clocks to the CPU, Flash, and SRAM will be stopped and the
system clocks to the peripherals are enabled. Each module may disable the module clocks
locally at the module level. In stop mode, all clocks to the system will be stopped.
During stop mode, there are several options for enabling/disabling the PLL and/or crystal
oscillator (OSC); each of these options requires a compromise between wakeup recovery
time and stop mode power. The PLL may be disabled during stop mode. A wakeup time of
up to 200 µs is required for the PLL to re-lock. The OSC may also be disabled during stop
mode. The time required for the OSC to restart is dependent upon the startup time of the
crystal used. Power consumption can be reduced in stop mode by disabling either or both
of these functions via the SYNCR[STMPD] bits.
The external CLKOUT signal may be enabled during low-power stop (if the PLL is still
enabled) to support systems using this signal as the clock source.
The system clocks may be enabled during wakeup from stop mode without waiting for the
PLL to lock. This eliminates the wakeup recovery time, but at the risk of sending a
potentially unstable clock to the system. It is recommended, if this option is used, that the
PLL frequency divider is set so that the targeted system frequency is no more than half the
maximum allowed. This will allow for any frequency overshoot of the PLL while still
keeping the system clock within specification.
In external clock mode, there are no wait times for the OSC startup or PLL lock.
During wakeup from stop mode, the Flash clock will always clock through 16 cycles before
the system clocks are enabled. This allows the Flash module time to recover from the
low-power mode. Thus, software may immediately continue to fetch instructions from the
Flash memory.
MOTOROLA
Chapter 7. Power Management
7-11

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