Gpt Input Capture/Output Compare Select Register (Gptios) - Motorola ColdFire MCF5281 User Manual

Table 20-3. GPT Modules Memory Map (continued)
IPSBAR Offset
GPTA GPTB
0x1A_0010 0x1B_0010
0x1A_0011 0x1Bb_0011
0x1A_0012 0x1B_0012
0x1A_0013 0x1B_0013
0x1A_0014 0x1B_0014
0x1A_0015 0x1B_0015
0x1A_0016 0x1B_0016
0x1A_0017 0x1B_0017
0x1A_0018 0x1B_0018
0x1A_0019 0x1B_0019
0x1A_001A 0x1B_001A
0x1A_001B 0x1B_001B
0x1A_001C 0x1B_001C
0x1A_001D 0x1B_001D
0x1A_001E 0x1B_001E
0x1A_001F 0x1B_001F
1
S = CPU supervisor mode access only.
2
Writes have no effect, reads return 0s, and the access terminates without a transfer error exception.
20.5.1 GPT Input Capture/Output Compare
Select Register (GPTIOS)
Field
Reset
R/W
Address
Figure 20-2. GPT Input Capture/Output Compare Select Register (GPTIOS)
MOTOROLA Chapter 20. General Purpose Timer Modules (GPTA and GPTB)
GPT Channel 0 Register High (GPTC0H)
GPT Channel 0 Register Low (GPTC0L)
GPT Channel 1 Register High (GPTC1H)
GPT Channel 1 Register Low (GPTC1L)
GPT Channel 2 Register High (GPTC2H)
GPT Channel 2 Register Low (GPTC2L)
GPT Channel 3 Register High (GPTC3H)
GPT Channel 3 Register Low (GPTC3L)
Pulse Accumulator Control Register (GPTPACTL)
Pulse Accumulator Flag Register (GPTPAFLG)
Pulse Accumulator Counter Register High (GPTPACNTH)
Pulse Accumulator Counter Register Low (GPTPACNTL)
GPT Port Data Register (GPTPORT)
GPT Port Data Direction Register (GPTDDR)
7
—
IPSBAR + 0x401A_0000, 0x401B_0000
Bits 7–0
(2)
Reserved
GPT Test Register (GPTTST)
4 3
0000_0000
R/W
Memory Map and Registers
Access
—
0
IOS
1
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
20-5