Motorola ColdFire MCF5281 User Manual page 780

Motorola microcontroller user's manual
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Address
IPSBAR + 0x00_0000
IPSBAR + 0x00_0040
IPSBAR + 0x00_0080
IPSBAR + 0x00_0100
IPSBAR + 0x00_0140
IPSBAR + 0x00_0180
IPSBAR + 0x00_01C0
IPSBAR + 0x00_0200
IPSBAR + 0x00_0240
IPSBAR + 0x00_0280
IPSBAR + 0x00_0300
IPSBAR + 0x00_0340
IPSBAR + 0x00_0400
IPSBAR + 0x00_0440
IPSBAR + 0x00_0480
IPSBAR + 0x00_04C0
IPSBAR + 0x00_0C00
IPSBAR + 0x00_0D00
IPSBAR + 0x00_0F00
IPSBAR + 0x00_1000
IPSBAR + 0x00_1400
IPSBAR + 0x10_0000
IPSBAR + 0x11_0000
IPSBAR + 0x12_0000
IPSBAR + 0x13_0000
IPSBAR + 0x14_0000
IPSBAR + 0x15_0000
IPSBAR + 0x16_0000
IPSBAR + 0x17_0000
IPSBAR + 0x18_0000
IPSBAR + 0x19_0000
IPSBAR + 0x1A_0000
IPSBAR + 0x1B_0000
IPSBAR + 0x1C_0000
IPSBAR + 0x1D_0000
IPSBAR + 0x400_0000
A-2
Table A-2. Module Memory Map Overview
Global Interrupt Acknowledge Cycles
Fast Ethernet Controller (Registers and MIB RAM)
Fast Ethernet Controller (FIFO Memory)
Reset Controller, Chip Configuration, and Power Management
Programmable Interval Timer 0
Programmable Interval Timer 1
Programmable Interval Timer 2
Programmable Interval Timer 3
General Purpose Timer A
General Purpose Timer B
CFM (Flash) Control Registers
CFM (Flash) Memory for IPS Reads and Writes
MCF5282 User's Manual
Module
System Control Module
SDRAM Controller
Chip Selects
DMA (Channel 0)
DMA (Channel 1)
DMA (Channel 2)
DMA (Channel 3)
UART0
UART1
UART2
2
I
C
QSPI
DMA Timer 0
DMA Timer 1
DMA Timer 2
DMA Timer 3
Interrupt Controller 0
Interrupt Controller 1
Ports
Clock Module
Edge Port
Watchdog Timer
QADC
FlexCAN
Size
64 bytes
64 bytes
128 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
64 bytes
256 bytes
256 bytes
256 bytes
1 K
1K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
512K
MOTOROLA

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