Port Clear Output Data Register (7-Bit); Port Clear Output Data Registers (4-Bit); Clrn (8-Bit,7-Bit, 6-Bit, And 4-Bit) Field Descriptions - Motorola ColdFire MCF5281 User Manual

7
Field —
Reset
R/W: R
Address
Figure 26-15. Port Clear Output Data Register (7-bit)
7
Field —
Reset
R/W: R
Address
Figure 26-16. Port Clear Output Data Registers (6-bit)
7
Field
Reset
R/W:
Address
Figure 26-17. Port Clear Output Data Registers (4-bit)
CLRn register bits are described in Table 26-6.
Table 26-6. CLRn (8-bit,7-bit, 6-bit, and 4-bit) Field Descriptions
Register
8-bit
7-bit
6-bit
4-bit
7-bit
6-bit
4-bit
MOTOROLA
6 5
CLRn6 CLRn5
IPSBAR + 0x10_0049 (CLRQS)
6 5
CLRn5
IPSBAR + 0x10_0048 (CLRAS), 0x10_004A (CLRSD)
—
R
IPSBAR + 0x10_004B (CLRTC), 0x10_004C (CLRTD), 0x10_004D (CLRUA)
Bits Name
7–0 CLRnx
6–0
5–0
3–0
7 —
7–6
7–4
Chapter 26. General Purpose I/O Module
4 3
CLRn4 CLRn3 CLRn2
0000_0000
R/W
4 3
CLRn4 CLRn3 CLRn2
0000_0000
R/W
4 3
CLRn3 CLRn2
0000_0000
Port n clear output data register bits.
1 Never returned for reads; no effect for writes
0 Always returned for reads; clears corresponding PORTn bit
for writes
Reserved, should be cleared.
Memory Map/Register Definition
2 1 0
CLRn1 CLRn0
2 1 0
CLRn1 CLRn0
2 1 0
CLRn1 CLRn0
R/W
Description
26-13