Mii Transmit Signal Timing Diagram; Mii Async Inputs Timing Diagram; Mii Async Inputs Signal Timing - Motorola ColdFire MCF5281 User Manual

Fast Ethernet AC Timing Specifications
Table 33-18 lists MII transmit channel timings.
Num
M5 ETXCLK to ETXD[3:0], ETXEN, ETXER invalid
M6 ETXCLK to ETXD[3:0], ETXEN, ETXER valid
M7 ETXCLK pulse width high
M8 ETXCLK pulse width low
1
ETXCLK, ETXD0, and ETXEN have the same timing in 10 Mbit 7-wire interface mode.
Figure 33-11 shows MII transmit signal timings listed in Table 33-18.
ETXCLK (input)
ETXD[3:0] (outputs)
ETXEN
ETXER
Figure 33-11. MII Transmit Signal Timing Diagram
33.12.3 MII Async Inputs Signal Timing (ECRS and ECOL)
Table 33-19 lists MII asynchronous inputs signal timing.
Num
1
M9 ECRS, ECOL minimum pulse width
1
ECOL has the same timing in 10 Mbit 7-wire interface mode.
Figure 33-12 shows MII asynchronous input timings listed in Table 33-19.
ECRS, ECOL
Figure 33-12. MII Async Inputs Timing Diagram
33-22
Table 33-18. MII Transmit Signal Timing
1
Characteristic
M5
M6
Table 33-19. MII Async Inputs Signal Timing
Characteristic
MCF5282 User's Manual
Min
5
—
35%
35%
M7
M8
Min
1.5
M9
Max Unit
— ns
25 ns
65% ETXCLK period
65% ETXCLK period
Max Unit
— ETXCLK period
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