Registers; Memory Map And Registers; Edge Port Module Memory Map - Motorola ColdFire MCF5281 User Manual

11.4 Memory Map and Registers

This subsection describes the memory map and register structure.
11.4.1 Memory Map
Refer to Table 11-2 for a description of the EPORT memory map. The EPORT has an
IPSBAR offset for base address of 0x0013_0000.
IPSBAR
Offset
0x0013_0000
0x0013_0002 EPORT Data Direction Register (EPDDR)
0x0013_0004 EPORT Data Register (EPDR)
0x0013_0006 EPORT Flag Register (EPFR)
1
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only
addresses have no effect and result in a cycle termination transfer error.
2
Writing to reserved address locations has no effect, and reading returns 0s.

11.4.2 Registers

The EPORT programming model consists of these registers:
• The EPORT pin assignment register (EPPAR) controls the function of each pin
individually.
• The EPORT data direction register (EPDDR) controls the direction of each one of
the pins individually.
• The EPORT interrupt enable register (EPIER) enables interrupt requests for each pin
individually.
• The EPORT data register (EPDR) holds the data to be driven to the pins.
• The EPORT pin data register (EPPDR) reflects the current state of the pins.
• The EPORT flag register (EPFR) individually latches EPORT edge events.
MOTOROLA
Table 11-2. Edge Port Module Memory Map
Bits 15–8
EPORT Pin Assignment Register (EPPAR)
Chapter 11. Edge Port Module (EPORT)
Memory Map and Registers
Bits 7–0
EPORT Interrupt Enable Register (EPIER)
EPORT Pin Data Register (EPPDR)
2
Reserved
1
Access
S
S
S/U
S/U
11-3