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Chapter 1
Overview
This chapter provides an overview of the MCF5282 microprocessor features, including the
major functional components.
1.1
MCF5282 Key Features
A block diagram of the MCF5282 is shown in Figure 1-1. The main features are as follows:
• Static Version 2 ColdFire variable-length RISC processor
— Static operation
— On-chip 32-bit address and data path
— Processor core and bus frequency up to 80 MHz
— Sixteen general-purpose 32-bit data and address registers
— ColdFire ISA_A with extensions to support the user stack pointer register, and
four new instructions for improved bit processing
— Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to
support 32-bit signal processing algorithms
— Illegal instruction decode that allows for 68K emulation support
• System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging
— Real time debug support, with one user-visible hardware breakpoint register (PC
and address with optional data) that can be configured into a 1- or 2-level trigger
• On-chip memories
— 2-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache
— 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and
non-core bus masters (e.g., DMA, FEC) with standby power supply support
— 512 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses
(256 Kbytes on the MCF5281)
– This product incorporates SuperFlash® technology licensed from SST.
MOTOROLA
Chapter 1. Overview
1-1
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