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DMA references in this section refer to the FEC's DMA
engine. This DMA engine is for the transfer of FEC data only,
and is not related to the DMA controller described in
Chapter 16, "DMA Controller Module," nor to the DMA
timers
(DTIM0–DTIM3)."
The RAM is the focal point of all data flow in the Fast Ethernet Controller and is divided
into transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSR
register. User data flows to/from the DMA block from/to the receive/transmit FIFOs.
Transmit data flows from the transmit FIFO into the transmit block and receive data flows
from the receive block into the receive FIFO.
The user controls the FEC by writing, through the SIF (Slave Interface) module, into
control registers located in each block. The CSR (control and status register) block provides
global control (e.g. Ethernet reset and enable) and interrupt handling registers.
The MII block provides a serial channel for control/status communication with the external
physical layer device (transceiver). This serial channel consists of the EMDC (Management
Data Clock) and EMDIO (Management Data Input/Output) lines of the MII interface.
The DMA block provides multiple channels allowing transmit data, transmit descriptor,
receive data and receive descriptor accesses to run independently.
The Transmit and Receive blocks provide the Ethernet MAC functionality (with some
assist from microcode).
The Message Information Block (MIB) maintains counters for a variety of network events
and statistics. It is not necessary for operation of the FEC but provides valuable counters
for network management. The counters supported are the RMON (RFC 1757) Ethernet
Statistics group and some of the IEEE 802.3 counters. See Section 17.5.3, "MIB Block
Counters Memory Map" for more information.
17.4 Functional Description
This section describes the operation of the FEC, beginning with the hardware and software
initialization sequence, then the software (Ethernet driver) interface for transmitting and
receiving frames.
Following the software initialization and operation sections are sections providing a
detailed description of the functions of the FEC.
MOTOROLA
NOTE
described
in
Chapter 21,
Chapter 17. Fast Ethernet Controller (FEC)
Functional Description
"DMA
Timers
17-5
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