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Operation
register and loaded into the top empty receiver holding register position of the FIFO. Thus,
data flowing from the receiver to the CPU is quadruple-buffered.
In addition to the data byte, three status bits, parity error (PE), framing error (FE), and
received break (RB), are appended to each data character in the FIFO; OE (overrun error)
is not appended. By programming the ERR bit in the channel's mode register (UMR1n),
status is provided in character or block modes.
USRn[RxRDY] is set when at least one character is available to be read by the CPU. A read
of the receive buffer produces an output of data from the top of the FIFO stack. After the
read cycle, the data at the top of the FIFO stack and its associated status bits are popped and
the receiver shift register can add new data at the bottom of the stack. The FIFO-full status
bit (FFULL) is set if all three stack positions are filled with data. Either the RxRDY or
FFULL bit can be selected to cause an interrupt or DMA request.
The two error modes are selected by UMR1n[ERR] as follows:
• In character mode (UMR1n[ERR] = 0, status is given in the USRn for the character
at the top of the FIFO.
• In block mode, the USRn shows a logical OR of all characters reaching the top of
the FIFO stack since the last
characters reach the top of the FIFO stack. Block mode offers a data-reception speed
advantage where the software overhead of error-checking each character cannot be
tolerated. However, errors are not detected until the check is performed at the end of
an entire message—the faulting character is not identified.
In either mode, reading the USRn does not affect the FIFO. The FIFO is popped only when
the receive buffer is read. The USRn should be read before reading the receive buffer. If all
three receiver holding registers are full, a new character is held in the receiver shift register
until space is available. However, if a second new character is received, the contents of the
the character in the receiver shift register is lost, the FIFOs are unaffected, and USRn[OE]
is set when the receiver detects the start bit of the new overrunning character.
To support flow control, the receiver can be programmed to automatically negate and assert
URTSn, in which case the receiver automatically negates URTSn when a valid start bit is
detected and the FIFO stack is full. The receiver asserts URTSn when a FIFO position
becomes available; therefore, overrun errors can be prevented by connecting URTSn to the
UCTSn input of the transmitting device.
The receiver can still read characters in the FIFO stack if the
receiver is disabled. If the receiver is reset, the FIFO stack,
URTSn control, all receiver status bits, and interrupts, and
DMA requests are reset. No more characters are received until
the receiver is reenabled.
23-24
RESET ERROR STATUS
NOTE
MCF5282 User's Manual
command. Status is updated as
MOTOROLA
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