Core Watchdog Control Register (Cwcr); Cwcr Field Description; Core Watchdog Timer Delay - Motorola ColdFire MCF5281 User Manual

Register Descriptions
Field CWE
Reset
R/W
Address
Figure 8-4. Core Watchdog Control Register (CWCR)
Bits Name
7 CWE Core watchdog enable.
0 SWT disabled.
1 SWT enabled.
6 CWRI Core watchdog reset/interrupt select.
0 If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt level for
the CWT is programmed in the interrupt control register 7 (ICR7) of INTC0.
1 A CWT time-out generates a soft reset to the entire device.
5–3 CWT[2:0] Core watchdog timing delay. These bits select the timeout period for the CWT as shown in Table 8-6.
At system reset, the CWT field is cleared signaling the minimum time-out period but the watchdog is
disabled (CWCR[CWE] = 0).
2 CWTA Core watchdog transfer acknowledge enable.
0 CWTA Transfer acknowledge disabled.
1 CWTA Transfer Acknowledge enabled. After one CWT time-out period of the unacknowledged
assertion of the CWT interrupt, the transfer acknowledge asserts, which allows CWT to terminate
a bus cycle and allow the interrupt acknowledge to occur.
1 CWTAVAL Core watchdog transfer acknowledge valid.
0 CWTA Transfer Acknowledge has not occurred.
1 CWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit.
0 CWTIF Core watchdog timer interrupt flag.
0 CWT interrupt has not occurred
1 CWT interrupt has occurred. Write a 1 to clear the interrupt request.
8-8
7 6 5
CWRI CWT[2:0]
Table 8-5. CWCR Field Description
Table 8-6. Core Watchdog Timer Delay
CWT [2:0]
000
001
010
011
100
101
110
111
MCF5282 User's Manual
3 2
CWTA CWTAVAL
0000_0000
R/W
IPSBAR + 0x011
Description
CWT Time-Out Period
9
2 Bus clock frequency
11
2 Bus clock frequency
13
2 Bus clock frequency
15
2 Bus clock frequency
19
2 Bus clock frequency
23
2 Bus clock frequency
27
2 Bus clock frequency
31
2 Bus clock frequency
1 0
CWTIC
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