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The desired QSPI_CLK baud rate is related to the system clock and QMR[BAUD] by the
following expression:
QMR[BAUD] = f
Table 22-2. QSPI_CLK Frequency as Function of System Clock and Baud Rate
22.4.3 Transfer Delays
The QSPI supports programmable delays for the QSPI_CS signals before and after a
transfer. The time between QSPI_CS assertion and the leading QSPI_CLK edge, and the
time between the end of one transfer and the beginning of the next, are both independently
programmable.
The chip select to clock delay enable bit in command RAM, QCR[DSCK], enables the
programmable delay period from QSPI_CS assertion until the leading edge of QSPI_CLK.
QDLYR[QCD] determines the period of delay before the leading edge of QSPI_CLK. The
following expression determines the actual delay before the QSPI_CLK leading edge:
QSPI_CS-to-QSPI_CLK delay = QDLYR[QCD]/f
QDLYR[QCD] has a range of 1–127.
When QDLYR[QCD] or QCR[DSCK] equals zero, the standard delay of one-half the
QSPI_CLK period is used.
The command RAM delay after transmit enable bit, QCR[DT], enables the programmable
delay period from the negation of the QSPI_CS signals until the start of the next transfer.
The delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to complete
conversion. There are two transfer delay options: the user can choose to delay a standard
period after serial transfer is complete or can specify a delay period. Writing a value to
QDLYR[DTL] specifies a delay period. QCR[DT] determines whether the standard delay
period (DT = 0) or the specified delay period (DT = 1) is used. The following expression is
used to calculate the delay:
MOTOROLA
Chapter 22. Queued Serial Peripheral Interface (QSPI) Module
/ [2 × (desired QSPI_CLK baud rate)]
SYS
QMR [BAUD]
2
4
8
16
32
255
System Clock
66.67 MHz
16.5 MHz
8.25 MHz
4.125 MHz
2.063 MHz
1.031 MHz
129.4 kHz
SYS
Operation
22-7
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