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23.5.6.1 Interrupt and DMA Request Initialization
23.5.6.1.1
Setting up the UART to Generate Core Interrupts
The list below gives the steps needed to properly initialize the UART to generate an
interrupt request to the core.
1. Initialize ICRx register in the interrupt controller (ICR13 for UART0, ICR14 for
UART1, and ICR15 for UART2)
2. Unmask appropriate bits in IMR in the interrupt controller (bits 13-15 for
UART0-UART2 respectively)
3. Verify DMAREQC (in SCM) does not assign UARTs to DMA channels
4. Initialize interrupts in the UART, see Table 23-13
23.5.6.1.2
Setting up the UART to Request DMA Service
The UART DMA request pin uses its interrupt pin to connect to the DMA. The user must
mask the UART interrupt in the interrupt control register when DMA requests are required.
The DMA should be configured for external requests (using the DMAREQC register) and
the source address set to the UART's receive buffer (URB).
The UART may request DMA transfers on FIFO not empty or FIFO full. The user selects
the request source by setting bit 6 in the UART's mode register 1 (UMR1). Setting UMR1
bit 6 = 0 allows DMA request on FIFO not empty, while setting UMR1 bit 6 = 1 allows
DMA requests on FIFO full. The user should then set bit 1 in the UART interrupt mask
register (UIMR[FFULL]).
In the case where DMA requests are set for UART FIFO full condition, once all the FIFO
stack positions are filled with data, the UART asserts its DMA request signal (via its
interrupt pin). Once the first data byte is read from the FIFO, the DMA request signal is
negated, and the FIFO stack is popped. However, the DMA may read the full contents of
the FIFO stack (if the DMA byte count register is set to 3 and the DMA control register is
not set for cycle steal).
MOTOROLA
Table 23-13. UART Interrupts
Register
Bit
UMR1x
6
RxIRQ
UIMRx
7
Change of State (COS)
UIMRx
2
Delta Break
UIMRx
1
RxFIFO Full
UIMRx
0
TxRDY
Chapter 23. UART Modules
Interrupt
Operation
23-29
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