Address Breakpoint Registers (Ablr, Abhr) - Motorola ColdFire MCF5281 User Manual

Bits Name
2–0 TM Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental
information for each transfer type.
TT = 00 (normal mode):
000 Explicit cache line push
001 User data access
010 User code access
011 Reserved
100 Reserved
101 Supervisor data access
110 Supervisor code access
111 Reserved
TT = 10 (emulator mode):
0xx–100 Reserved
101 Emulator mode data access
110 Emulator mode code access
111 Reserved
TT = 11 (acknowledge/CPU space transfers):
000 CPU space access
001–111 Interrupt acknowledge levels 1–7
These bits also define the TM encoding for BDM memory commands (for backward compatibility).

29.4.3 Address Breakpoint Registers (ABLR, ABHR)

The ABLR and ABHR, shown in Figure 29-6, define regions in the processor's data
address space that can be used as part of the trigger. These register values are compared
with the address for each transfer on the processor's high-speed local bus. The trigger
definition register (TDR) identifies the trigger as one of three cases:
1. Identical to the value in ABLR
2. Inside the range bound by ABLR and ABHR inclusive
3. Outside that same range
31
Field
Reset
R/W Write only. ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG instruction
and via the BDM port using the
ABLR is accessible in supervisor mode as debug control register 0x0D using the WDEBUG instruction and via the
BDM port using the
DRc[4–0]
Figure 29-6. Address Breakpoint Registers (ABLR, ABHR)
MOTOROLA
Table 29-5. AATR Field Descriptions (continued)
and
RDMREG WDMREG
command.
WDMREG
0x0D (ABLR); 0x0C (ABHR)
Chapter 29. Debug Support
Description
Address
—
commands.
Programming Model
0
29-9