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10.1.1 Interrupt Controller Theory of Operation
To support the interrupt architecture of the 68K/ColdFire programming model, the
combined 63 interrupt sources are organized as 7 levels, with each level supporting up to 9
prioritized requests. Consider the priority structure within a single interrupt level (from
highest to lowest priority) as shown in Table 10-1.
The level and priority is fully programmable for all sources except interrupt sources 1–7.
Interrupt source 1–7 (from the Edgeport module) are fixed at the corresponding level's
midpoint priority. Thus, a maximum of 8 fully-programmable interrupt sources are mapped
into a single interrupt level. The "fixed" interrupt source is hardwired to the given level,
and represents the mid-point of the priority within the level. For the fully-programmable
interrupt sources, the 3-bit level and the 3-bit priority within the level are defined in the
8-bit interrupt control register (ICRnx).
The operation of the interrupt controller can be broadly partitioned into three activities:
• Recognition
• Prioritization
• Vector Determination during IACK
10.1.1.1 Interrupt Recognition
The interrupt controller continuously examines the request sources and the interrupt mask
register to determine if there are active requests. This is the recognition phase.
10.1.1.2 Interrupt Prioritization
As an active request is detected, it is translated into the programmed interrupt level, and the
resulting 7-bit decoded priority level (IRQ[7:1]) is driven out of the interrupt controller.
MOTOROLA
Table 10-1. Interrupt Priority Within a Level
ICR[2:0]
111
110
101
100
—
Fixed Midpoint Priority
011
010
001
000
Chapter 10. Interrupt Controller Modules
68K/ColdFire Interrupt Architecture Overview
Interrupt
Priority
Sources
7 (Highest)
8-63
6
8-63
5
8-63
4
8-63
1-7
3
8-63
2
8-63
1
8-63
0 (Lowest)
8-63
10-3
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